Micro Channel Architecture

The Micro Channel architecture consists of an address bus, a data bus, an arbitration bus, a set of interrupt signals, and support signals. It uses synchronous and asynchronous procedures for data transfer between memory, I/O devices, and a controlling master. The controlling master can be a DMA controller, the system master (system processor), or a bus master. The features of the Micro Channel architecture are:

Micro Channel Participants

All Micro Channel participants are either masters or slaves. There are three types of masters and three types of slaves.

An adapter can incorporate either a master function, a slave function, or a combination of both. For example, an adapter might be designed to operate primarily as a DMA slave. However, it would also respond to certain I/O read and I/O write operations from the system master, making it an I/O slave. If the adapter contains RAM or ROM that is in the memory address space, it would be a memory slave when that memory was accessed.

Masters

A master is a participant that drives the address bus and data transfer control signals that cause data transfer to or from a slave. The channel supports up to 16 masters. The central arbitration control point and the Micro Channel arbitration procedure control ownership of the channel. The central arbitration control point grants ownership at the end of the arbitration procedure to highest-priority requester. The three types of masters are:

Slaves

A slave is a participant that sends and receives data under the control of a master. The slave responds to signals that are driven by the master. A slave is selected by the controlling master using Micro Channel procedures. The channel supports 8-, 16- and 32-bit data bus size in a slave. The data port size (8-, 16-, or 32-bits) describes the maximum width of the data transfer. For example, a 32-bit slave can support 8-, 16- 24-, or 32-bit data transfers. During a data transfer cycle, an 8-bit data port on a 32-bit slave acts like an 8-bit slave. The three types of slaves are:

Addressing Model

The Micro Channel addressing model consists of a memory address space and an I/O address space. During an I/O cycle, the 64KB I/O address space is addressed by the low-order 16 bits of the address bus. During a memory cycle, the memory address space is addressed by the address bus. The signals used for an address of up to 4GB are MADE 24 , M/-IO , and A0 through A31 of the address bus. An address of up to 16MB uses A0 through A23 plus MADE 24 and M/-IO .

Micro Channel Buses and Signals

The Micro Channel architecture consists of:

Throughout this document, a minus sign (-) in front of a signal name indicates that the signal is active when it is at a low-voltage level. When no minus sign appears, the signal is active when it is at a high-voltage level. For example, -CMD specifies the signal is active low. Also, ARB/-GNT is in the ARB state when it is at a high level and is in the -GNT state when it is at a low level.

Arbitration Bus and Associated Signals

The arbitration bus and associated signals allow arbitrating participants (the system master, bus masters, and DMA slaves) to request and gain ownership of the channel. The resolution of multiple arbitration requests results in granting ownership of the channel to the highest-priority requester.

ARB0 - ARB3:
Arbitration Bus: These signals make up the arbitration bus. They are driven by the system master, bus masters, and DMA slaves to present their arbitration level when requesting ownership of the channel. ARB0 (least significant) through ARB3 (most-significant) support up to 16 arbitration levels.

The highest value of the arbitration bus (hex F) has the lowest priority, and the lowest value (hex 0) has the highest priority. To participate in the arbitration procedure, an arbitrating participant must present its arbitration level immediately after the rising edge of ARB/-GNT . All arbitrating participants monitor the arbitration bus, and those with lower priority arbitration levels withdraw them by not driving less-significant arbitration bits.

The arbitration level of the highest-priority requester is valid on the arbitration bus after a settling time.

After the channel is granted to the highest-priority requester, that requester continues to drive its arbitration level on the bus.

ARB/-GNT:
Arbitrate/-Grant: Only the central arbitration control point drives this signal. The negative-to-positive transition of ARB/-GNT initiates an arbitration cycle. When in the ARB state, this signal indicates an arbitration cycle is in progress. When in the -GNT state, this signal indicates the acknowledgment from the central arbitration control point to the arbitrating participants and the DMA controller that channel ownership has been granted. This signal is driven to the ARB state by the central arbitration control point following the end of transfer (EOT).

Note: The system master can perform data transfers during arbitration ( ARB/-GNT in the ARB state).

-BURST:
-Burst: This signal is optionally driven by the winning arbitrating participant or the DMA controller after ARB/-GNT is driven to the -GNT state. This signal indicates to the central arbitration control point that the controlling master will use the channel for one or more consecutive data transfer cycles. This type of data transfer is called burst transfer .

-PREEMPT:
-Preempt: This signal is used by arbitrating participants to request use of the channel through arbitration. Any arbitrating participant that requires ownership of the channel drives -PREEMPT active, causing an arbitration cycle to occur. When a participant is granted control of the channel, it stops driving -PREEMPT . All arbitrating participants that have not been granted ownership keep their requests pending by continuing to drive -PREEMPT active. All masters and DMA slaves that use burst transfer must receive -PREEMPT .

Address Bus and Associated Signals

The address bus and the associated signals are used by the controlling master to assert the memory address or the I/O address ( M/-IO ), to enable a slave to latch the address and status signals ( -S0, -S1 ), and to indicate that the memory address is greater than 16MB.

A0 - A23:
Address Bits 0 through 23: These lines, along with A24 through A31 , make up the address bus. These lines are driven by the controlling master to address memory, I/O slaves, and, optionally, DMA slaves. A0 is the least-significant bit and A23 is the most-significant bit. These 24 address lines allow access of up to 16MB of memory. Only the lower 16 address lines ( A0 through A15 ) are for I/O operations, and all 16 lines must be decoded by the I/O slave. Valid addresses, generated by the controlling master, are unlatched on the channel and, if required, must be latched by the slaves using either the leading or trailing edge of -ADL or the leading edge of -CMD .

A24 - A31:
Address Bits 24 through 31: These lines, along with A0 through A23 are driven by the controlling master to address memory attached to the channel. A0 is the least-significant bit and A31 is the most-significant bit. These additional address lines allow access of up to 4GB of memory. Valid addresses, generated by the controlling master, are unlatched on the channel and, if required, must be latched by the slaves using either the leading or trailing edge of -ADL or the leading edge of -CMD .

Note: A0 - A31 are used to transfer data during a 64-bit streaming data cycle.

-ADL:
-Address Decode Latch: This signal, driven by the controlling master, is provided as a convenient way for the slave to latch valid address decodes and status bits.

-APAREN:
-Address Parity Enable: This optional signal is driven active by the controlling master when the master places an address on the bus. This signal indicates to a slave that address parity is supported.

APAR0 - APAR3:
Address Parity Bits 0 through 3: These optional signals are driven by the controlling master when an address is placed on the address bus. These signals represent the odd parity of the address bits on the address bus during both read and write operations. (Odd parity is the condition where the total number of 1s in a byte of data, including the parity bit, is odd.) APAR(0) represents the odd parity of A(0-7) . APAR(1) represents the odd parity of A(8-15) . APAR(2) represents the odd parity of A(16-23) . APAR(3) represents the odd parity of A(24-31) .

During both read and write operations, a master generates a parity bit for each valid address byte, and the receiving slave optionally performs the parity checking to ensure the integrity of the address.

Note: APAR0 - APAR3 represent data parity during 64-bit streaming data cycle when -DPAREN is active.

APAR(0) represents the odd parity of D(32-39) . APAR(1) represents the odd parity of D(40-47) . APAR(2) represents the odd parity of D(48-55) . APAR(3) represents the odd parity of D(56-63) .

-CD SFDBK (n):
-Card Selected Feedback: This signal is driven active by the selected slave as a positive acknowledgement of the slave's selection. The (n) indicates this signal is unique to each channel connector (one independent signal per connector). This signal is unlatched. The slave does not drive -CD SFDBK during the configuration procedure ( -CD SETUP active). Any slave, not on an adapter card, provides a signal equivalent to the -CD SFDBK signal.

Note: Memory that contains diagnostic code must not drive -CD SFDBK during the diagnostic operation.

MADE 24:
Memory Address Enable 24: This signal is driven by the controlling master and decoded by all memory slaves, regardless of the size of their address-space. When this signal is active, A24 - A31 are undefined.

M/-IO:
Memory/-Input Output: This signal is driven by the controlling master and decoded by all slaves. This signal selects a memory cycle or an I/O cycle. When this signal is in the M state, a memory cycle is selected. When this signal is in the -IO state, an I/O cycle is selected.

-SFDBKRTN:
Selected Feedback Return: This optional signal is generated by the system logic from the AND of the -CD SFDBK( n ) signals being driven by slaves. This signal is a positive acknowledgement to the master from the slave that the slave is at the address specified by the master. Masters that support address parity must receive this signal. The -CD SFDBK signal from each slave, not on an adapter card, is included in the AND to generate -SFDBKRTN .

Data Bus and Associated Signals

The data bus is used to transfer either 8, 16, 24, or 32 bits of data. The associated signals indicate the amount of data transferred by the master in a single transfer cycle, the size of the slave's data port, and the type (read or write) of the data transfer.
D0 - D15:
Data Bits 0 through 15: These lines, along with D16 - D31 , make up the data bus. The data bus is driven by any master or slave that is transferring data. These lines ( D0 - D15 ) provide data bits 0 through 15. D0 is the least-significant bit; D15 is the most-significant bit. The 16-bit transfers from the controlling master to an 8-bit slave are converted by the controlling master to two 8-bit transfers, and are transmitted on lines D0 through D7 . An 8-bit slave must use D0 through D7 to communicate with the controlling master.

D16 - D31:
Data Bits 16 through 31: These lines, along with D0 - D15 , make up the data bus. The data bus is driven by any master or slave that is transferring data. These lines ( D16 - D31 ) provide data bits 16 through 31. D0 is the least-significant bit; D31 is the most-significant bit. The 32-bit transfers from the controlling master to an 8-bit slave are converted to four 8-bit transfers by the controlling master, and are transmitted on lines D0 through D7 . The 32-bit transfers from the controlling master to a 16-bit slave are converted to two 16-bit transfers by the controlling master, and are transmitted on lines D0 through D15 .

-BE0 - -BE3:
-Byte Enable 0 through 3: These signals are used during data transfers with 32-bit slaves to indicate which data bytes are valid on the data bus. Data transfers of 8, 16, 24, or 32 contiguous bits are controlled by -BE0 through -BE3 during transfers involving 32-bit slaves only. These signals are driven by the controlling master when TR 32 is inactive, and by the central translator logic (for those operations involving a 16-bit master with a 32-bit slave) when TR 32 is active. These signals are not latched on the bus and, if required, are latched by 32-bit slaves.

-CD DS 16 (n):
-Card Data Size 16: This signal is driven by 16-bit and 32-bit slaves to indicate a 16-bit or 32-bit data port at the location addressed. The (n) indicates this signal is unique to each channel connector (one independent signal per connector). This signal is derived from an unlatched address decode. -CD DS 16 is not driven by 8-bit slaves and is inactive for an 8-bit data port. Any slave, not on an adapter card, provides a signal equivalent to the -CD DS 16 signal.

-CD DS 32 (n):
-Card Data Size 32: This signal, along with -CD DS 16 , is driven by 32-bit slaves to indicate a 32-bit data port at the location addressed. The (n) indicates this signal is unique to a channel connector position (one independent signal per connector). -CD DS 32 is derived from an unlatched address decode. -CD DS 32 is inactive for an 8- or 16-bit data port. Any slave, not on an adapter card, provides a signal equivalent to the -CD DS 32 signal.

CD CHRDY (n):
Channel Ready: This signal is normally active (ready) and is driven inactive (not ready) by a slave to allow additional time to complete a channel cycle. The (n) indicates this signal is unique to each channel connector (one independent signal per connector). Any slave, not on an adapter card, provides a signal equivalent to the -CD CHRDY signal.

During a read cycle, a slave ensures that data is valid within the time specified after releasing the signal to a ready state. The slave also holds the data long enough for the controlling master to sample the data. A slave can also use this signal during a write cycle if more time is needed to store the data. This signal is initially driven from a valid unlatched address decode and status active.

CHRDYRTN:
Channel Ready Return: This signal is the AND of CD CHRDY ( n ) . It is driven by the system logic. If all slaves drive CD CHRDY active, this signal is active. CHRDYRTN allows the controlling master to monitor the ready information. The -CD CHRDY signal from each slave, not on an adapter card, is included in the AND to generate -CHRDYRTN .

-CMD:
-Command: This signal is driven by the controlling master and is used to define when data on the data bus is valid. The trailing edge of this signal indicates the end of the bus cycle. During write cycles, the data is valid as long as -CMD is active. During read cycles, the data is valid after the leading edge, but before the trailing edge, of -CMD and is held on the bus until after -CMD goes inactive. Slaves can latch address and status information with the leading edge of -CMD .

-DPAREN:
-Data Parity Enable: This optional signal is driven active by the participant when data is placed on the data bus. This signal indicates that the data parity signals are valid.

Note: APAR(0) - APAR(3) represent data parity during 64-bit streaming data cycles when -DPAREN is active.

DPAR0 - DPAR1:
Data Parity Bits 0 and 1: These optional signals are driven by the participant when data is placed on the data bus. These signals represent the odd parity of the data bits on the data bus during both read and write operations. (Odd parity is the condition where the total number of 1s in a byte of data, including the parity bit, is odd.) DPAR(0) represents the odd parity of D(0-7) . DPAR(1) represents the odd parity of D(8-15) .

During write operations, a master generates a parity bit for each data byte being transferred, and the receiving slave optionally performs the parity checking to ensure the integrity of the data. During read operations, a slave generates a parity bit for each valid data byte, and the receiving master optionally performs the parity checking to ensure the integrity of the data.

DPAR2 - DPAR3:
Data Parity Bits 2 and 3: These optional signals are driven by the participant when data is placed on the data bus. These signals represent the odd parity of the data bits on the data bus during both read and write operations.

DPAR(2) represents the odd parity of D(16-23) . DPAR(3) represents the odd parity of D(24-31) .

During write operations, a master generates a parity bit for each data byte being transferred, and the receiving slave optionally performs the parity checking to ensure the integrity of the data. During read operations, a slave generates a parity bit for each valid data byte, and the receiving master optionally performs the parity checking to ensure the integrity of the data.

-DS 16 RTN:
-Data Size 16 Return: This signal is driven by the system logic. This signal is the AND of -CD DS 16 ( n ) from each channel connector. If any slave drives its -CD DS 16 active, this signal is active.

This signal allows the controlling master to monitor the information about the selected slave's data port size. The -CD DS 16 signal from each slave, not on an adapter card, is included in the AND to generate -DS 16 RTN .

-DS 32 RTN:
-Data Size 32 Return: This signal is driven by the system logic. This signal is the AND of -CD DS 32 ( n ) from each channel connector. If any slave drives its -CD DS 32 active, this signal is active. This signal allows the controlling master to monitor the information about the selected slave's data port size. The -CD DS 32 signal from each slave, not on an adapter card, is included in the AND to generate -DS 32 RTN . 
     -DS 16      -DS 32
     RTN         RTN          Data Port Size
     1           1            8-Bit Data Port
     1           0            Not Valid
     0           1            16-Bit Data Port
     0           0            32-Bit Data Port

-MSDR:
-Multiplexed Streaming Data Request: This optional signal is driven by a slave to indicate to the controlling master that the slave is capable of 64-bit streaming data transfers.

-SBHE:
-System Byte High Enable: This signal is driven by the controlling master to indicate and enable transfers of data on D8 - D15 . It is used with A0 to distinguish between high-byte transfers ( D8 - D15 ) and low-byte transfers ( D0 - D7 ) and double-byte (16-bit) transfers to 16-bit data ports. All 16-bit slaves receive this signal.

-SD STROBE:
-Streaming Data Strobe: The controlling master and the slave use this signal to clock data on and off the data bus. This optional signal is driven by the controlling master. This signal also indicates to the slave that the controlling master supports streaming data.

-SDR(0):
-Streaming Data Request 0: This optional signal is driven by a slave to indicate to the controlling master that the slave is capable of streaming data, and also indicates the maximum clocking rate the slave supports.

-SDR(1):
-Streaming Data Request 1: This optional signal is driven by a slave to indicate to the controlling master that the slave is capable of streaming data, and also indicates the maximum clocking rate the slave supports. 
     -SDR(0)     -SDR(1)      Decoded Streaming Rate
     1           1            Basic Transfer Cycle
     0           1            10 MHz maximum (100 ns minimum cycle)
     0           0            20 MHz maximum (50 ns minimum cycle)
     1           0            Reserved

-S0, -S1:
-Status 0, -Status 1: These status signals are driven by the controlling master to indicate the start of a data transfer cycle and also define the type of data transfer. When used with M/-IO , memory read or write cycles are distinguished from I/O read or write cycles. These signals are latched by the slave, as required, using the leading edge of -CMD , or the leading or trailing edge of -ADL.

Data is transferred to or from the data bus based on -CMD and a latched decode of the address, the status lines ( -S0 exclusive-OR -S1 ), and M/-IO .

Slaves must support a full decode of -S0 and -S1 . The following table shows the states of M/-IO , -S0 , and -S1 in decoding I/O and memory read and write commands. 

     M/-IO       -S0          -S1         Function
     0           0            0           (see note below)
     0           0            1           I/O Write Command
     0           1            0           I/O Read Command
     0           1            1           Inactive
     1           0            0           (see note below)
     1           0            1           Memory Write Command
     1           1            0           Memory Read Command
     1           1            1           Inactive

Note: These decodes are used in the 20 MHz streaming data transfer. Some systems execute system specific basic transfer procedures with both status signals active.

An I/O write command instructs an I/O slave to receive the data from the data bus. An I/O read command instructs an I/O slave to drive its data onto the data bus.

A memory write command instructs a memory slave to receive the data from the data bus. A memory read command instructs a memory slave to drive its data onto the data bus.

-TC:
-Terminal Count: This signal is driven by the DMA controller and provides a pulse during a read or write command to the DMA slave to indicate that the terminal count of the current DMA channel has been reached. This indicates to the DMA slave that this is the last cycle to be performed. -TC is driven active on the channel during DMA operations only.

TR 32:
Translate 32: This signal is driven inactive by 32-bit controlling masters and received by the central translator logic. The signal indicates to the central translator logic that the controlling master is performing data steering. TR 32 can also be received by any 32-bit slave.

Interrupt Signals

-IRQ 3-7, -IRQ 9-12, and -IRQ 14-15:
-Interrupt Request: An interrupt request is generated when an I/O slave drives one of the ]interrupt requestä signals low. These signals make up the set of interrupt signals. The polarity of these signals makes it possible for multiple slaves to concurrently share the same interrupt level.

Other Micro Channel Signals

AUDIO:
Audio Sum Node: This analog signal is the sum of all the audio signals being driven. It is used to drive audio signals from an adapter to the system audio output and other adapters. The frequency response of the audio signal is 50 Hz to 10 kHz ’ 3 dB. The maximum signal amplitude is 2.5 Vac peak-to-peak, at a dc offset of 0.0 Vdc ’ 50 millivolts. The noise level is limited to a maximum of 50 millivolts peak-to-peak.

AUDIO GND:
Audio Ground: This is the analog ground return signal for the audio subsystem.

-CD SETUP (n):
-Card Setup: This signal is driven by system logic to individually select channel connectors. The (n) indicates this signal is unique to each channel connector (one independent signal per connector). When this signal is activated, a specific channel connector is selected, and, if an adapter is present, access is gained to configuration data at that connector. The adapter ID and configuration data is obtained by an I/O read during a setup cycle; the configuration data is stored by an I/O write during a setup cycle.

-CHCK:
-Channel Check: This signal is driven active by a slave to report an exception condition, and optionally, it can be driven by a master.

CHRESET:
Channel Reset: This signal is generated by the system logic to reset or initialize all adapters at power-on or when a low voltage condition is detected. The system can also activate this signal under program control.

OSC:
Oscillator: This signal is a high-speed clock driven by the system logic, with a frequency of 14.31818 MHz +/-0.01%. The high-level pulse width (more than 2.3 Vdc) and the low-level pulse width (less than 0.8 Vdc) must not be less than 20 nanoseconds each.

-REFRESH:
-Refresh: This signal is driven by the system logic and is used to indicate that a memory refresh operation is in progress. Memory slaves that do not need to perform refresh operations do not need to receive this signal.

Channel Signal Groups (Analog)

AUDIO and AUDIO GND are the only analog signals in the Micro Channel. The AUDIO signal is a connection between all audio drivers and receivers on the bus. The AUDIO subsystem can support single and multiple drivers as well as single and multiple receivers. The receivers can be either AC or DC coupled. Each AUDIO driver has a source impedance of 1200 +/- 20%. Each AUDIO receiver has an input impedance of not less than 7500 ohms.

The system provides a path to the system speaker. The system provides a 600 +/- 20% impedance from AUDIO to AUDIO GND . The AUDIO GND must not be used for any analog circuitry other than the AUDIO subsystem.

Channel Signal Groups (Digital)

The following figure lists the digital Micro Channel signals and shows what type of driver or receiver is required. The 'audio' and 'audio ground' signals are analog signals. When a Micro Channel adapter combines the functions of bus masters and slaves, the signals driven and received by the adapter are a superset of the selected functions.

For example:

The central arbitration control point, central steering logic, and central translator logic are packaged within the system logic. The system logic also includes circuitry for memory refresh, the oscillator, and channel reset.

The signals for the 16-bit adapter are a subset of the signals for the 32-bit adapter. 

 Signal          System  DMA     Bus     DMA     Memory  I/O     Driver
 Name            Master  Cntlr   Master  Slave   Slave   Slave   Type

                 D/R     D/R     D/R     D/R     D/R     D/R     Signal
                                                                 Group
  A(0-15)        D/-     D/-     D/-     -/O     -/R     -/R     TS (1)
  A(16-23)       D/-     D/-     D/-     -/-     -/R     -/-     TS (1)
  A(24-31)       */-     */-     */-     -/-     -/*     -/-     TS (1)
 -ADL            D/-     D/-     D/-     -/O     -/O     -/O     TS (1)
  APAR(0-3)      O/-     O/-     O/-     -/O     -/O     -/O     TS (2)
 -APAREN         O/-     O/-     O/-     -/O     -/O     -/O     TS (2)
  ARB(0-3)       O/O     -/R     D/R     D/R     -/-     -/-     OC (5)
  ARB/-GNT       D/-     -/R     -/R     -/R     -/-     -/-     BD (4)
 -BE(0-3)        */-     */-     */-     -/*     -/*     -/*     TS (1)
 -BURST          O/R     D/R     O/-     O/-     -/O     -/O     OC (5)
  CD CHRDY (n)   -/R     -/-     -/-     O/-     O/-     O/-     TP (3)
 -CD DS 16 (n)   -/R     -/-     -/-     $/-     $/-     $/-     TP (3)
 -CD DS 32 (n)   -/*     -/-     -/-     */-     */-     */-     TP (3)
 -CD SETUP (n)   D/-     -/@     -/@     -/@     -/@     -/@     TP (8)
 -CD SFDBK (n)   -/R     -/-     -/-     D/-     D/-     D/-     TP (3)
 -CHCK           -/R     O/R     O/R     O/-     O/-     O/-     OC (6)
  CHRDYRTN       D/-     -/R     -/R     -/-     -/-     -/-     BD (4)
  CHRESET        D/-     -/R     -/R     -/R     -/R     -/R     BD (4)
 -CMD            D/-     D/-     D/-     -/R     -/R     -/R     TS (1)
  D(0-7)         D/R     D/R     D/R     D/R     D/R     D/R     TS (2)
  D(8-15)        D/R     D/R     D/R     $/$     $/$     $/$     TS (2)
  D(16-31)       */*     */*     */*     */*     */*     */*     TS (2)
  DPAR(0)        O/O     O/O     O/O     O/O     O/O     O/O     TS (2)
  DPAR(1)        O/O     O/O     O/O     O/O     O/O     O/O     TS (2)
  DPAR(2-3)      O/O     O/O     O/O     O/O     O/O     O/O     TS (2)
 -DPAREN         O/O     O/O     O/O     O/O     O/O     O/O     TS (2a)
 -DS 16 RTN      D/-     -/R     -/R     -/-     -/-     -/-     BD (4)
 -DS 32 RTN      */-     -/*     -/*     -/-     -/-     -/-     BD (4)
 -IRQ (N)        O/R     O/-     O/O     O/-     O/-     O/-     OC (6)
  M/-IO          D/-     D/-     D/-     -/R     -/R     -/R     TS (1)
  MADE 24        D/-     D/-     D/-     -/-     -/R     -/-     TS (1)
 -MSDR           -/O     -/O     -/O     O/-     O/-     O/-     TS (1)
  OSC            D/-     -/O     -/O     -/O     -/O     -/O     CD (7)
 -PREEMPT        D/R     -/-     D/O     D/O     -/-     -/-     OC (5)
 -REFRESH        D/-     -/-     -/-     -/-     -/O     -/-     BD (4)
 -S0,-S1         D/*     D/-     D/-     -/R     -/R     -/R     TS (1)
 -SBHE           D/*     D/-     D/-     -/#     -/#     -/#     TS (1)
 -SFDBKRTN       O/-     -/O     -/O     -/-     -/-     -/-     BD (4)
 -SD STROBE      O/-     O/-     O/-     -/O     -/O     -/O     TS (1)
 -SDR(0)         -/O     -/O     -/O     O/-     O/-     O/-     TS (1)
 -SDR(1)         -/O     -/O     -/O     O/-     O/-     O/-     TS (1)
 -TC             -/-     D/-     -/-     -/R     -/-     -/-     TS (1)
  TR 32          */R     */-     */-     -/O     -/O     -/O     TS (1)

 - KEY -
 D = Drive Enabled    OC = Open Collector     # = Required for 16-bit devices
 O = Optional         TS = Tri-State          $ = Required for 16- or 32-bit
 R = Receive Enabled  TP = Totem Pole             devices
 - = Not Implemented  BD = Bus Driver         * = Required for 32-bit devices
 CD = Clock Driver    N = IRQ(9-12,14,15,3-7) @ = -CD SETUP is received by all
                                                  adapters

The following table and notes apply to the driver and receiver options above. 

Signal Group  Driver Type      Capacity   Loading   Capacitance
1             Tri-State        24 mA      20 pF     240 pF
2             Tri-State        24 mA      20 pF     240 pF
2a            Tri-State        24 ma      20 pF     240 pF
3             Totem Pole        6 mA      20 pF      40 pF
4             Bus Driver       24 mA      20 pF     240 pF
5             Open Collector   24 mA      15 pF     200 pF
6             Open Collector   24 mA      20 pF     240 pF
7             Clock Driver     24 mA      15 pF     200 pF
8             Totem Pole or     6 mA      50 pF     Not
              Tri-State                             Applicable

Notes:

  1. The maximum loading current is 1.6 mA per channel connector, except signal group 5. The maximum loading current of group 5 is 1.0 mA per channel connector.
  2. An open collector can be either an open-collector device or a tri-state device wired with the input grounded and using the enable line of the tri-state device to control the output.
  3. For good signal quality, the net length on the adapter for any control signal driven or received on the adapter should not exceed 2 inches.
  4. A Tri-state driver can be used on -REFRESH as long as all timing requirements are met for this signal. 
Signal  Driver                   Recommended   Recommended    Note
Group   Type                     Resistor      Resistor
                                 to +5 Vdc     to Ground
1       Tri-State                1 K ohms      2 K ohms
2       Tri-State                1 K ohms      2 K ohms       2
2a      Tri-State                470 ohms      940 ohms       4
3       Totem Pole               2.2 K ohms    4.4 K ohms
4       Bus Driver               2.2 K ohms    4.4 K ohms
5       Open Collector           470 ohms      940 ohms       3
6       Open Collector           1 K ohms      2 K ohms       2
7       Clock Driver             1 K ohms      2 K V
8       Totem Pole or Tri-State  None          None

Notes:

  1. All termination resistors have a recommended tolerance of 5 percent. The termination resistors are provided by system logic for all signals except -CD SETUP (N) . Adapters that receive -SDR0, -SDR1, -MSDR, and -SD STROBE provide a pull-up resistor for each signal received. A 20K V resistor pulled to +5 Vdc is recommended.
  2. The group 2 and 6 terminator provides a rise time (0.0 to 2.0 Vdc) of 200 ns or less.
  3. The group 5 terminator provides a rise time (0.0 to 2.0 Vdc) of 70 ns or less.
  4. The group 2a terminator provides a rise time (0.0 to 2.0 Vdc) of 90 ns or less.

Micro Channel Procedures

The Micro Channel procedures, as well as data steering, are described in the following pages.

Arbitration

The arbitration procedure provides the functions to resolve multiple requests for control of the channel.

Arbitration consists of local arbiters, the arbitration bus and the associated signals, and a central arbitration control point.

The arbitration bus is a parallel bus that consists of four lines ARB(0-3) , supporting up to 16 arbitration levels. These arbitration levels are hex 0 through hex F; level hex 0 is the highest priority, level hex F is the lowest priority. The master with level hex F is always the default master. No two active arbiters will be assigned the same arbitration level at the same time.

If no -PREEMPT is driven, the arbitration level defaults to hex F and the default master gains control of the channel.

Channel Ownership

Channel ownership is controlled by the central arbitration control point based on prioritized arbitration of up to 16 devices. These arbitrating devices can be the system master, bus masters, or DMA slaves. If either a bus master or the system master wins the arbitration, it controls the bus and becomes the controlling master. If a DMA slave wins the arbitration, the supporting DMA controller becomes the controlling master.

If a system master is also the default master, the system master controls the Micro Channel when the channel is not controlled by any other master.

Central Arbitration Control Point

The central arbitration control point controls arbitration cycles using three arbitration signals: -PREEMPT , ARB/-GNT , and -BURST .

Arbitrating participants (local arbiters) drive -PREEMPT active to request use of the channel. An arbiter can activate -PREEMPT asynchronously. However, an arbiter must have -PREEMPT activated before the beginning of an arbitration cycle to participate in that cycle. If an arbiter drives -PREEMPT active when an arbitration cycle is in progress, it must wait for the next arbitration cycle before driving its arbitration level onto the arbitration bus. An arbiter that activates -PREEMPT while ARB/-GNT is in the -GNT state should (but is not required to) participate in the next arbitration cycle. An arbiter that has -PREEMPT active for at least 20 nanoseconds prior to ARB/-GNT being driven to the -GNT state must participate in the next arbitration cycle (and all following arbitration cycles) until it wins control of the channel.

The central arbitration control point initiates an arbitration cycle by driving ARB/-GNT to the ARB state.

The requesting local arbiters then drive their 4-bit arbitration level onto the arbitration bus. When a local arbiter sees a more-significant bit low on the arbitration bus (other than those driven low by itself), it stops driving its less-significant bits onto the arbitration bus. The local arbiter driving the lowest arbitration level (highest priority) thereby wins control of the channel when ARB/-GNT goes to the -GNT state.

When a master is granted control of the channel, it is required to initiate a transfer cycle or an abort cycle. An exception is the system master that wins the channel be default. The system must continue to function correctly when multiple consecutive grants default to arbitration level hex F.

Arbitrating participants with multiple data transfers to perform signal the central arbitration control point by driving -BURST active. -BURST is held active until all transfers have been completed or until another participant drives -PREEMPT active. When preempted, the controlling master or DMA slave must release the channel and signal the end of transfer within 7.8 microseconds.

The end of transfer (EOT) is indicated by the trailing edge of -S0 , -S1 , -BURST , or -CMD , whichever occurs last. When the central arbitration control point detects an EOT condition, it drives ARB/-GNT to the ARB state, initiating the next arbitration cycle.

When ARB/-GNT is in the ARB state, bus masters and DMA controllers disable all of their channel drivers except -PREEMPT and ARB(0-3) . Slaves, including bus masters and DMA controllers responding as slaves, must be capable of driving the channel when addressed.

During exception conditions, the central arbitration control point can gain control of the channel by driving ARB/-GNT to the ARB state independently of an EOT condition.

Note: While ARB/-GNT is in the ARB state, the system master can perform data transfers and system logic can perform refresh operations. Selected slaves must respond independently of the state of ARB/-GNT

Local Arbiters

Participants requesting the use of the channel implement logic that allows all competing participants to recognize the winner. This logic is known as a local arbiter. An arbitrating participant competes for control of the channel only if it has driven -PREEMPT active before ARB/-GNT goes to the ARB state. A competing local arbiter drives its arbitration level onto the arbitration bus, then compares its arbitration level, on a bit-by-bit basis, with the value appearing on the arbitration bus beginning with the most significant bit, ARB3 . If the competing local arbiter detects a mismatch on one of the bits, it immediately stops driving its less-significant bits. If the local arbiter subsequently recognizes a match on that bit, it resumes driving its less-significant bits until another mismatch is detected. The following is an example of an arbitration cycle.

  1. Two local arbiters with arbitration levels 1010 and 0101 (hex A and 5) compete for the channel. Both local arbiters sense ARB/-GNT being driven to the ARB state and drive their arbitration levels on the bus, which now appears as 0000.
  2. The first local arbiter (1010) detects a mismatch on ARB3 and stops driving all less-significant arbitration bits ( ARB2 and ARB0 in this case).
  3. The second local arbiter (0101) detects a mismatch on ARB2 and stops driving its less-significant arbitration bit ( ARB1 , in this case). The arbitration bus now shows 0111.
  4. The second local arbiter now sees a match on ARB2 and resumes driving ARB1 of the arbitration bus.
  5. The arbitration bus now shows a value of 0101, and the second local arbiter wins the arbitration cycle when ARB/-GNT is driven to the -GNT state.
  6. The winning local arbiter continues to drive its arbitration level on the arbitration bus throughout the grant period until the channel is released and ARB/-GNT is driven to the ARB state.

Burst Transfer

To use burst transfer, a controlling master or a DMA slave activates -BURST after being granted the channel. -BURST is held active until after the start of the last cycle of the burst transfer.

Preemption

When an arbitrating participant requires the channel, it activates -PREEMPT . The following diagram shows -PREEMPT occurring during a burst transfer.

The preempted burst transfer sequence is as follows:

  1. Participant A has control of the channel and has driven -BURST active.
  2. Participant B drives -PREEMPT active.
  3. Participant A, still in control of the channel, recognizes -PREEMPT active and signals the EOT condition within 7.8 microseconds. Participant A does not participate in the next arbitration cycle if its fairness feature is enabled.
  4. When the central arbitration control point recognizes the EOT, it drives ARB/-GNT to the ARB state.
  5. The arbitration cycle begins.
  6. When ARB/-GNT is in the -GNT state, Participant B gains control of the channel.
  7. Participant B, the preempting participant, removes -PREEMPT in response to gaining control of the channel.

Arbitrating masters should maximize use of the channel within the 7.8 microsecond limit from -PREEMPT going active. If a master or a DMA slave does not release the channel by presenting EOT within 7.8 microseconds after -PREEMPT is driven active, a channel time-out can occur, creating an exception condition.

Fairness Feature and the Inactive State

All bursting participants must support the fairness feature. Fairness forces the bursting participant to equitably share the channel time with the other participants. An optional configuration field in programmable option select (POS) can be used to disable the fairness feature.

When a bursting participant with control of the channel senses an active -PREEMPT , it must release the channel within the specified time (even if the fairness feature is disabled). If its fairness feature is enabled, the participant must enter the inactive state unless -PREEMPT was inactive while that participant owned the channel. If -PREEMPT was inactive while that participant had control, it is not required to enter the inactive state but must release the channel. In the inactive state, the bursting participant will not drive -PREEMPT active or participate in arbitration.

To exit the inactive state, the arbitrating participant must wait for -PREEMPT to go inactive. The participant then waits for a specified time after the trailing edge of status (status active to inactive) before driving -PREEMPT active. It is possible for multiple arbitrating participants to be in the inactive state concurrently.

Note: The participant exits the inactive state independently of the state of ARB/-GNT .

System Master and Arbitration

The system master and the central arbitration control point can work together to improve use of the channel by overlapping a system master data transfer with arbitration as follows.

When the system master is the controlling master and -PREEMPT is active, ARB/-GNT can be driven to the ARB state. After the arbitration cycle is completed and the system master has signalled EOT, ARB/-GNT is driven to the -GNT state.

The system master can execute cycles during arbitration. When the arbitration cycle is completed, ARB0 - ARB3 can be checked to see if the winning arbitration level is the system master's arbitration level. If the winning arbitration level is the system master's arbitration level, ARB/-GNT can be driven to the -GNT state while the system master is executing a bus operation.

Data Transfer

The data transfer procedures are used to transfer data between a controlling master and the selected slave. The three types of data transfer procedures are:

Each procedure defines the signal sequences and the signal timing specifications used in the procedure. Data transfer occurs only during the data transfer cycle defined by the procedure. A cycle is one or more data transfers, occurring during the time between the leading edge of -CMD and the trailing edge of -CMD . The data transfer cycle address selects either an I/O-address-space address or a memory-address-space address, under the control of M/-IO .

A controlling master or a DMA slave can drive -BURST , to indicate to the central arbitration control point that one or more data transfer cycles will be used before the EOT occurs.

This section describes each procedure, the signal sequence for each procedure, and the signal timing specifications.

The system-specific technical manuals contain the signal sequence and timing specifications for matched-memory signals and auxiliary-video signals.

Basic Transfer

The three types of basic transfer cycles are:

Basic Transfer Procedure

All masters and DMA controllers transfer data with the same control sequence. The following covers the case of a write cycle. The signals appear in the following sequence:

  1. The master drives the address bus, MADE 24 , M/-IO , -APAREN , APAR(0-3) , TR 32 , and -REFRESH (if applicable) valid, beginning the cycle.
  2. In response to an unlatched decode of address, MADE 24 , and M/-IO , the selected slave returns:
  3. The master drives -S0 active ( -S1 inactive).
  4. In response to an unlatched decode of address, MADE 24 , M/-IO , and status, the selected slave drives CD CHRDY inactive if the cycle is to be extended.
  5. The master drives -ADL active. A slave can latch decodes of address, status, and M/-IO at the leading or trailing edge of -ADL . A DMA slave can also be selected by a latched decode of the same signals, using the arbitration level in place of the address.
  6. The master drives the write data onto the data bus and, if appropriate, drives -DPAREN active and DPAR(0-3) valid.
  7. The master drives -CMD active and -ADL inactive. A slave must latch the decodes of address, status, and M/-IO with the leading edge of -CMD if they were not latched with -ADL .
  8. If CD CHRDY has been driven inactive, the cycle is extended until CD CHRDY is driven active. The signal must not be held inactive longer than specified.
  9. The status signals become inactive and the address bus can change in preparation for the next cycle.
  10. In response to an address change, the slave updates the state of:
  11. The status signals and M/-IO can become valid in preparation for the next cycle.
  12. -CMD goes inactive and the selected slave receives the data from the data bus. The data transfer cycle is complete.
  13. The selected slave degates the data bus and data transfer control signals when it is no longer selected (status and -CMD are inactive).
Note: The changes to the address bus and status ( -S0, -S1 ) can be overlapped with the preceding cycle to minimize the impact of the memory access time.

Whether a default, a synchronous-extended, or an asynchronous-extended cycle is performed depends on how a slave uses CD CHRDY .

Abort Cycle

If a master begins a transfer cycle but must abort that cycle, -ADL and -CMD must not be activated, and -S0, -S1 must be activated with a minimum pulse width T2A. The T2A time allows the central arbitration control point to recognize EOT. -BURST , if active, is deactivated with status deactivation. Slaves must not latch CD CHRDY inactive until after the appearance of an active -ADL signal, and if the cycle is aborted, must release CD CHRDY with the deactivation of status.

Synchronous-Extended Cycle Timing (300 ns Minimum)

A synchronous-extended cycle occurs when a slave drives CD CHRDY inactive, then releases CD CHRDY synchronously within the specified time after the leading edge of -CMD .

Asynchronous-Extended Cycle Timing (>= 300 ns)

An asynchronous-extended cycle occurs when a slave drives CD CHRDY inactive, then releases CD CHRDY asynchronously.

Streaming Data Transfer

The streaming data procedure provides performance improvements over basic transfer procedures for block transfers, and supports data-transfer rates of up to 160MB per second. It provides for the transfer of a data block by using a single address followed by multiple 16-, 32-, or 64-bit data transfers within a single streaming data cycle. The data transfers are clock-synchronous and incorporate automatic speed matching between the controlling master and slave.

The streaming data procedure can be used for high speed data transfer between a controlling master and the selected slave. The streaming data procedure is transparent to devices that are not selected. Streaming data participants must support the basic transfer procedure to operate with nonstreaming-data participants.

Special rules apply to streaming data devices to ensure compatibility with nonstreaming-data participants. These include:

Note: Streaming data participants must support a fully-functional operation with nonstreaming-data participants, independent of the state of the Streaming Data Enable fields.

Implementing and using streaming data transfer is optional to masters. Implementing and indicating streaming data transfer capabilities is optional to slaves.

Streaming Data Procedure (16- or 32-Bit)

A 16- or 32-bit streaming data transfer cycle is initiated as either a 16- or 32-bit basic data transfer cycle, and all rules associated with those procedures apply. The following is an example of a 16- or 32-bit streaming data write cycle. The signals appear in the following sequence:

  1. The master drives the address bus, MADE 24 , M/-IO , -APAREN , and APAR(0-3) valid to begin the cycle.
  2. In response to an unlatched decode of address, MADE 24 , and M/-IO , the selected slave returns:
  3. The master drives -S0 active ( -S1 inactive).
  4. In response to an unlatched decode of address, MADE 24 , M/-IO , and status, the selected slave drives CD CHRDY inactive, if the cycle is to be extended.
  5. A 32-bit master (or the central translator logic for a 16-bit master in a 32-bit system) drives the byte enable signals. -BE(0-3) is driven to binary 0011 by the central translator logic, or -BE(0-3) is driven to binary 0000 by a 32-bit master.

    Note: Because 16- and 32-bit streaming data operations are aligned on four-byte boundaries, A0 , A1 , and -SBHE equal a binary 000.

  6. The master drives -ADL valid. A slave can latch decodes of address, status, and M/-IO at the leading or trailing edge of -ADL .
  7. The slave drives -SDR(0,1) active.

    Note: When the slave does not drive -SDR(0) , or -SDR(1) active, the controlling master meets the basic transfer timings.

  8. The master drives the write data onto the bus and, if supported, drives -DPAREN active and DPAR(0-3) valid.
  9. The master drives -CMD active and -ADL inactive. A slave must latch the decodes of address, status, and M/-IO with the leading edge of -CMD if they were not latched with -ADL .
  10. If CD CHRDY has been driven inactive, the cycle is extended until CD CHRDY is driven active. CD CHRDY must not be held inactive longer than specified.
  11. The controlling master indicates 10 MHz streaming data can be performed by starting -SD STROBE . The master indicates 20 MHz streaming data cycles by starting -SD STROBE and then driving the second Status line active. The master drives the second Status line active if the slave drives -SDR(0,1) to a binary 00 (or to a binary 10). The first -SD STROBE period is greater than 50 ns for a 20 MHz streaming data transfer.

    Note: If CHRDYRTN is active, -SD STROBE can be activated concurrently with -CMD . -SD STROBE is used by both the controlling master and slave to transfer data, with data being clocked on and off the bus on the falling clock edge and clocked off the bus on the next falling clock edge. The operation proceeds with new data being placed on the bus every time -SD STROBE makes a high-to-low transition.

  12. The master drives status inactive. The slave drives -SDR(0,1) inactive.
  13. The address bus can change in preparation for the next cycle.
  14. In response to an address change, the slaves update the state of:
  15. The status signals and M/-IO can become valid in preparation for the next cycle.
  16. The master stops driving -SD STROBE .
  17. On the last transfer, the controlling master drives -CMD inactive, and the selected slave gates the data off the bus. The transfer cycle is complete.

Streaming Data Procedure (64-Bit)

A 64-bit streaming data transfer cycle is initiated as a 32-bit basic transfer cycle, and all the rules associated with this procedure apply. The following is an example of a 64-bit streaming data write cycle. The signals appear in the following sequence:

  1. The master drives the address bus, MADE24 , M/-IO , -APAREN , and APAR(0-3) valid to begin the cycle.
  2. In response to an unlatched decode of address, MADE24 , and M/-IO , the selected slave returns:
  3. The master drives -S0 active ( -S1 inactive).
  4. In response to an unlatched decode of address, MADE24 , M/-IO , and status, the selected slave drives CD CHRDY inactive, if the cycle is to be extended.
  5. A 32-bit master drives -BE(0-3) to binary 0000 (64-bit streaming data transfers are not performed by 16-bit masters).

    Note: Because 64-bit operations are aligned on an eight-byte boundary, A0 , A1 , and -SBHE equal binary 000.

  6. The master drives -ADL active. A slave can latch decodes of address, status, and M/-IO at the leading or trailing edge of -ADL .
  7. The slave drives -SDR(0,1) to indicate its transfer speed capability and drives -MSDR active to indicate 64-bit capability.

    Note: When the slave does not drive -SDR(0) , or -SDR(1) active, the controlling master meets the basic transfer timings.

  8. The master drives the write data onto the data bus and, if supported, drives -DPAREN active and DPAR(0-3) valid.
  9. The master drives -CMD active and -ADL inactive. A slave must latch the decodes of address, status, and M/-IO with the leading edge of -CMD if they were not latched with -ADL .
  10. If CD CHRDY has been driven inactive, the cycle is extended until CD CHRDY is driven active. CD CHRDY must not be held inactive longer than specified.
  11. The controlling master indicates 10 MHz streaming data can be performed by starting -SD STROBE . The master indicates 20 MHz streaming data cycles by starting -SD STROBE and then driving the second Status line active. The master drives the second Status line active if the slave drives -SDR(0,1) to a binary 00 (or a binary 10). The first -SD STROBE period is greater than 50 ns for a 20 MHz streaming data transfer.

    The 64-bit streaming data transfer is indicated by driving -BE(0-3) inactive, driving data bits 32-63 of the eight byte transfer on the address bus, and, if -DPAREN is active, driving APAR(0-3) valid. -APAREN is driven inactive.

    Note: -SD STROBE is used by both the controlling master and the slave to transfer data; data is clocked on and off the address bus and the data bus on the falling clock edge and clocked off the address bus and the data bus on the next falling clock edge. The operation proceeds with the new data being placed on the address bus and the data bus each time -SD STROBE makes a high-to-low transition.

  12. Both the address bus and data bus are used for transferring data for the remainder of the cycle.
  13. The master drives status inactive. The slave drives -SDR(0,1) inactive.
  14. In response to data on the address bus, other slaves can drive -CD SFDBK , -CD DS 16 , -CD DS 32 , and CD CHRDY valid during the data transfer. The master should not monitor the state of these signals during the data transfer.
  15. On the last transfer, the controlling master drives -CMD inactive and the slave gates the data off the address bus and the data bus. The cycle is complete.

Streaming Data Transfer Rates

The amount of data transferred per -SD STROBE period is constant during streaming data transfer. The number of bytes transferred in one transfer cycle are listed below. 

Streaming Data
Master Size      16-Bit Slave   32-Bit Slave   64-Bit Slave
--------------   ------------   ------------   ------------
16-Bit           2              2              2
32-Bit           2              4              4
64-Bit           2              4              8

Note: When a slave requests a 10 MHz streaming data transfer, it must be prepared to support a minimum of two transfers. When a master initiates a 10 MHz streaming data transfer, it must be prepared to support a minimum of two transfers.

When a slave requests a 20 MHz streaming data transfer, it must be prepared to support a minimum of 4 transfers. When a master initiates 20 MHz streaming data transfers, it must be prepared to support a minimum of 4 transfers.

Address Bus Management

During 16 and 32 bit streaming data transfers, the address on the address bus and TR 32 are not changed until -SDR(0,1) is driven inactive. The controlling master and the slave must provide memory-address-space address management and I/O-address-space address management as follows:

Address Boundary Alignment

If the starting address is not a four-byte address boundary and a 16- or 32-bit streaming data procedure is going to be used, then the basic transfer procedure must be used to transfer data until the address has the correct boundary alignment. The controlling master must execute the basic transfer procedure to obtain address boundary alignment.

A slave can indicate streaming data capability, by driving -SDR(0,1) active, without checking address boundary alignment. Then the controlling master and the slave can use the streaming data procedure. The basic transfer procedure might also be required to complete the data transfer, even if the initial data address was a four-byte address boundary.

If the starting address is not on an eight-byte address boundary and a 64-bit streaming transfer procedure is going to be used basic transfer cycles are used to transfer data until the address has a correct boundary alignment. The basic transfer procedure might also be needed to complete the data transfer, even if the initial data address was a eight-byte address boundary.

Streaming Data Cycles

A master can perform streaming data transfers at 10 MHz when -SDR(0,1) is a binary 00, 01, or 10, and can perform the transfer at less than the requested width. A master can perform streaming data transfers at 20 MHz when -SDR(0,1) is a binary 00 or 10 and can perform the transfer at less than the requested width. The valid streaming data signal combinations from the selected slave are shown in the following table. 

-SDR #   -CD DS
0 1 #    16/32 #   -MSDR #   Type of Cycle Requested by Slave
1 1 #    X X #     X #       Basic Transfer
0 1 #    0 0 #     0 #       64-bit Streaming Data Transfer at 10 MHz max.
0 1 #    0 0 #     1 #       32-bit Streaming Data Transfer at 10 MHz max.
0 1 #    0 1 #     1 #       16-bit Streaming Data Transfer at 10 MHz max.
0 0 #    0 0 #     0 #       64-bit Streaming Data Transfer at 20 MHz max.
0 0 #    0 0 #     1 #       32-bit Streaming Data Transfer at 20 MHz max.
0 0 #    0 1 #     1 #       16-bit Streaming Data Transfer at 20 MHz max.
1 0 #    X X #     X #       Reserved

Both 16- and 32-bit masters can use streaming data procedures with either 16- or 32-bit slaves.

However, because the central translator logic does not perform data steering during a streaming data transfer, a 32-bit slave must perform the steering when streaming with a 16-bit master. (The 32-bit master does the steering for all data transfers with slaves having a smaller data port.)

The following describe how:

64-Bit Streaming Data Cycles

The 64-bit streaming data transfer can only be used between 64-bit streaming masters and 64-bit streaming slaves. The 64-bit streaming transfer is similar to the 32-bit streaming data transfer, but uses both the data bus and the address bus to achieve the 64-bit data transfer width.

The 64-bit cycle begins as a 32-bit basic transfer cycle. The selected slave responds by driving -CD DS 16 , -CD DS 32 , -SDR(0,1) and -MSDR valid to indicate that it supports 64-bit streaming operations. The data rate requested by the slave is indicated by -SDR(0,1) . -BE(0-3) are driven inactive by the master to indicate a 64-bit streaming-data procedure will be used. The master indicates 20 MHz streaming data transfers by driving the second Status line active. During a transfer to the slave, the master starts -SD STROBE and gates the data onto the data and address buses. During a transfer to the master, the master tri-states the address bus after driving -CMD active, and, after the trailing edge of -BE(0-3) , the slave gates the data onto the data and address buses. The least significant byte is D(0-7) and the most significant byte is A(24-31) .

The 64-bit streaming transfer then proceeds like a 32-bit streaming data transfer.

If -DPAREN has been driven active, the parity bits for data bytes zero through three are contained in DPAR(0-3), the parity bits for data bytes four through seven are contained in APAR(0-3) .

Deferred start of the 64-bit streaming transfer is supported, but data pacing is not available during 64-bit data streaming transfers.

Starting the Cycle

Streaming masters can drive -SD STROBE active at the same time as -CMD to minimize the overhead in starting the streaming data cycle. The propagation delay for the signals to and from the slave can delay the sample point of -SDR(0,1) and -MSDR until after -CMD and -SD STROBE have been activated. Therefore, if a slave requests a 10 MHz streaming data transfer and the master activated -SD STROBE , the master must perform at least two streaming data transfers. If 20 MHz streaming data transfers are supported by both the master and the slave, both must execute at least 4 streaming data transfers. If the slave does not request streaming data transfer and the master activated -SD STROBE , the operation defaults to a basic transfer cycle and the rules for deactivation of -S0, -S1 apply, as specified by the basic transfer procedure.

If 20 MHz streaming data transfers are supported by both the master and the slave, both must execute at least 4 streaming data transfers.

Deferring the Start of the Cycle

During a streaming data transfer, the slave may need more time at the start of the cycle to prepare for the transfer. The slave can defer the start of the transfer by driving CD CHRDY inactive. The controlling master delays the start of -SD STROBE until after CHRDYRTN goes active.

If -SDR(0,1) is not active within the time specified (T70A), the controlling master continues the cycle using basic transfer procedures. All specifications for the basic transfer procedure apply.

If -SDR(0,1) is active, after CHRDYRTN becomes active, the streaming data procedure can be invoked.

Pacing the Data

After a 16- or 32-bit streaming data cycle is started, CD CHRDY and CHRDYRTN pace the data transfer, allowing slaves to introduce momentary pauses in the data transfer. CD CHRDY is clocked simultaneously with data and makes state transitions following the high-to-low transition of -SD STROBE On each falling edge, the controlling master must inspect the state of CHRDYRTN . When CHRDYRTN is inactive during a read operation, it indicates that the slave did not have valid data in this clock period and that the transfer must be repeated. When CHRDYRTN is inactive during a write operation, it indicates the slave did not accept the data and that the transfer must be repeated.

Note: Data pacing by the slave is not supported during 64-bit streaming data cycles.

Data pacing by the slave is not supported during 20 MHz streaming data cycles. The master ignores CHRDYRTN once 20 MHz streaming data transfers have started.

If the slave has driven CD CHRDY inactive, it must not deactivate -SDR(0,1) .

When -MSDR is active, the slave cannot pace the transfer. The slave can use CD CHRDY only to delay the initiation of 64-bit transfers. Slaves that cannot meet the timing specifications for the 64-bit transfer must terminate the streaming data cycle. After -SD STROBE is being driven, the master ignores CHRDYRTN .

As the controlling source of CD CHRDY , the slave internally clocks its bus interface registers with the inversion of -SD STROBE . At the end of the cycle, the bus interface registers are clocked when -CMD goes high. The internal interface clock of the controlling master is conditional on CHRDYRTN being active.

To perform data transfer pacing, streaming masters can introduce momentary pauses in the data transfer by extending -SD STROBE . Data is transferred on the falling edge of -SD STROBE . The strobe period can be extended at either the high or low level, or both. This is done asynchronously to the edges of -SD STROBE .

Whenever the slave is not-ready ( CD CHRDY inactive), the master must continue to pulse -SD STROBE .

The actual data transfer will occur on the falling edge of -SD STROBE or (for the last transfer) the rising edge of -CMD once the slave becomes ready by driving CD CHRDY active.

Terminating the Cycle

Either the controlling master or the slave can terminate the streaming data procedure. If -PREEMPT has become active, the controlling master terminates the streaming data procedure within 7.8 microseconds and releases the channel at EOT. If the fairness feature is active, the preempted master enters the inactive state.

The controlling master can terminate a 10 MHz streaming data cycle by deactivating -S(0,1) on the data transfer before the desired stopping point. This can be done concurrently with the high-to-low transition of -SD STROBE . If -SDR(0,1) is inactive, the controlling master drives -CMD inactive at the point where the next -SD STROBE would have been. The slave must not drive -SDR(0,1) inactive while driving CD CHRDY inactive during 16- or 32-bit transfers. If -SDR(0,1) is active and CD CHRDY is inactive, it indicates that the slave is not ready, and the controlling master cannot terminate the cycle.

Direct Memory Access Procedure

A direct memory access (DMA) operation is a specialized sequence of basic transfer procedure. It consists of a single transfer or a burst transfer between a DMA slave and a memory slave. The following lists only those definitions, signal sequences, and timing specifications that are different from or additional to those of a basic transfer cycle.

Read and Write Operations

During a DMA write operation, the DMA slave provides the data and the memory slave stores it.

During a DMA read operation, the memory slave provides the data and the DMA slave stores it. If the slave is unable to provide or store data within the time specified for a normal operation, it extends the cycle by driving CD CHRDY inactive. To ensure the read data is valid, the slaves storing the data sample the data lines with reference to the trailing edge of the -CMD .

DMA Slave Selection

A DMA slave is selected by either its arbitration level or optionally by its I/O address, but not by both.

The default selection is by decode of the arbitration level, status ( -S0 exclusive-OR -S1 ), and an I/O cycle ( M/-IO in the -IO state). Selection by I/O address is by decode of the I/O address ( A0-A15 ), status ( -S0, -S1 ), and an I/O cycle ( M/-IO in the -IO state). When selection by I/O address is implemented for a DMA slave, a bit located in either configuration-data space or I/O address space is used to control the method of selection. All DMA slaves drive -CD SFDBK during the I/O portion of the DMA cycle for both selection methods.

Address During DMA Operation

During a memory cycle, the DMA controller drives the memory address on the address bus. During an I/O cycle, the DMA controller must drive a known I/O address on the bus. The I/O address must be that of the DMA slave, or hex FFFC or 0000.

Transfer Data Length

Normally, the DMA transfer length is an integral number of transfers of a width determined by the DMA slave's data port width. The data port address for a 16-bit DMA slave must be on an even address boundary; the address for a 32-bit DMA slave must be on a four-byte address boundary. The burden of supporting odd-length transfers is the responsibility of the DMA slave.

DMA Procedure

The two types of DMA procedures are:

Single Transfer

During a data transfer, the requesting DMA slave initiates the DMA operation by having its arbiter drive -PREEMPT active and arbitrate for the channel. On the low-to-high transition edge of ARB/-GNT (start of arbitration cycle), the DMA slave's priority level is placed on the arbitration bus. The DMA slave competes for use of the channel as defined in the arbitration procedure.

On the high-to-low transition edge of ARB/-GNT the DMA controller monitors the arbitration bus to determine if its DMA slave gained control of the channel. A match initiates a serial DMA operation in which the DMA controller drives the address lines during both cycles, as well as driving -S0, -S1, -CMD , and other control signals. The DMA controller also monitors -BURST , finds it inactive, and then activates -BURST (either on the channel, or through the system logic) to notify the central arbitration control point that consecutive cycles are required.

The DMA controller also manages the storage of data during the DMA read or DMA write operations for the consecutive cycles required by serial DMA transfers. Data count for data gated on or off the bus by the DMA slave is also maintained by the DMA controller.

Notes:

  1. The DMA controller might be required to perform multiple cycles for the data transfer to the memory slave, if the data port width of the memory slave is less than that of the DMA slave.
  2. DMA slaves using the single-transfer-type DMA procedure will not receive more data than is required to support their data port width (for example, 2 bytes to a 16-bit port).
  3. Consecutive transfers can be made with the DMA slave (as opposed to the serial sequences shown in the remainder of this section). The memory read or write cycles might not appear on the channel.

Burst Transfer (Multiple Transfer Cycles)

The method for transferring a block of data is similar to a single transfer DMA cycle, except that the local arbiter for the requesting DMA slave activates -BURST to request continued channel ownership for a burst operation. The central arbitration control point will not drive ARB/-GNT to the ARB state while -BURST is active. As in single-transfer DMA operations, the DMA controller drives the address, -S0 , -S1 , -CMD , and data transfer signals, as well as manages addresses and data transfer counts. The DMA controller also drives -BURST (either on the channel or through the system logic) jointly with the DMA slave for DMA write cycles. It does not drive -BURST active for burst DMA read cycles.

DMA Terminating Conditions

The DMA transfer operation is terminated by the EOT. At this time, a DMA slave can again request DMA service by arbitrating for use of the channel.

The terminating conditions for DMA transfers are:

Use of -BURST

When a bursting DMA slave wins the arbitration for the channel, it drives -BURST active. During default cycles, the DMA slave drives -BURST inactive when it detects status active for the last I/O cycle of this burst transfer. However, on sensing -SBHE and/or -BE(0-3) , the DMA slave might discover that it has one more cycle to perform. If so, it redrives -BURST active to continue the transfer.

During extended cycles, the DMA slave drives -BURST inactive within the specified time after the leading edge of -CMD .

If a burst transfer is terminated by the DMA controller, the DMA slave drives -BURST inactive within the specified time after the leading edge of -TC .

For DMA write cycles using burst transfers, the DMA controller drives -BURST active at the leading edge of -CMD for each I/O read and drives it inactive when it detects status active for the next memory write.

Interrupt Procedures

This section describes how all devices use interrupts. The procedure for sharing interrupts uses a request for interrupt services that is detected by the level of the interrupt request signal (level sensitive). These procedures involve the interaction between the hardware and an interrupt service routine.

To initiate an interrupt request, a device drives its -IRQ(N) active (N represents the assigned interrupt level for the device) and holds the signal active until it is reset by the interrupt service routine.

Each device provides an interrupt-pending bit within its address space. This bit is set by the device when it has an interrupt request pending and is reset by the interrupt handler when the interrupt request is serviced.

Note: The drivers for the interrupt signal must be disabled when the device is disabled.

An example of the sequence of the hardware and interrupt service routine interaction is shown in the following.

Hardware Operation

1. An interrupt condition causes the hardware to drive -IRQ(N) active and sets an interrupt-pending latch, which can be read by software.

Software Operation

2. A master begins executing code at the beginning of the appropriate chain of interrupt handlers.

3. The interrupt handler reads the interrupt-pending latch of the first device in the chain. If the latch is not set, the next device in the chain is tested. When the reporting device is detected, the handler executes the service routine.

4. The interrupt service routine operates the device hardware.

Hardware Operation

5. The device hardware resets the interrupt-pending latch and the interrupt request because of interrupt-service-routine actions.

Software Operation

6. The interrupt service routine completes the interrupt processing.

7. If another interrupt is pending ( -IRQ(N) driven active by another device), the sequence starts again at 1.

Refresh

The timing of the refresh operation is performed by system logic. -REFRESH is driven active during a memory-read operation to indicate that a refresh cycle is in progress. The refresh cycle is a basic transfer default cycle with -REFRESH active. The timing for -REFRESH is the same as that of the address bus.

Note: Adapters with registers that have destructive read-outs and are mapped into the memory address space should include -REFRESH in their address decode.

During a refresh operation, the nine low-order address bits are incremented for each refresh cycle to address the next byte to be refreshed. ( A0 changes after each refresh cycle; A8 changes after 256 cycles.) The address bits, A31 through A9 , might not change, but these bits will be stable during the refresh cycle. The signals -BE(0-3) and -SBHE are irrelevant (but stable) during the refresh cycle.

The refresh operation can occur in periodic intervals or in short bursts of multiple operations. The refresh rate is a minimum of 128 refresh cycles every 2 milliseconds.

Note: Time periods between refresh cycles can vary and should not be used as a timing mechanism.

Regardless of whether it decodes -REFRESH or not, a memory slave can perform a memory read operation during a refresh cycle and drive its data onto the data bus, provided its memory address is on the address bus.

Memory slaves that do not need to perform refresh operations do not need to receive this signal.

System Configuration

The adapter configuration procedure consists of:

The system master configures a system using setup cycles. The system configuration procedure supports the identification of the adapters that reside within a system (by reading the adapter IDs) and the configuration of those adapters (by writing configuration data). Configuration data consists of the following programmable fields:

Multiple Card Adapters

Multiple-card adapters are adapters that consist of a primary card and one or more secondary cards. The secondary cards are installed in the channel connectors adjacent to the primary card and can be on either, or both, sides of the primary card. The number of secondary cards is limited only by the number of connectors available.

The multiple-card adapter provides only one set of POS registers. Only the primary card responds to -CD SETUP .

The multiple-card adapter operates as a single adapter, and is completely enabled or disabled by the single set of POS registers.

Adapter Configuration Data

After initialization, the system must be able to access the configuration data written into adapter POS registers.

Adapters must always respond to setup cycles. After initialization, the ability to change the configuration data in the POS registers for an adapter is adapter dependent.

When its -CD SETUP is active, the adapter must provide access to its configuration data. This data is contained in its POS registers and is divided into multiple device-unique, read/write fields.

The following table shows the organization of the I/O address space used for POS operations. Setup functions respond to these addresses only when -CD SETUP is active. 

Address
(Hex)       Function
XXX0        POS Register 0 - Adapter Identification Byte (Low Byte)
XXX1        POS Register 1 - Adapter Identification Byte (High Byte)
XXX2        POS Register 2 - Option Select Data Byte 1
            Bit 0 is designated as Card Enable.
XXX3        POS Register 3 - Option Select Data Byte 2
XXX4        POS Register 4 - Option Select Data Byte 3
XXX5        POS Register 5 - Option Select Data Byte 4
            Bit 7 is designated as channel check.

            Bit 6 is designated as channel-check-status indicator.
XXX6        POS Register 6 - Subaddress Extension (Low Byte)
XXX7        POS Register 7 - Subaddress Extension (High Byte)

Bits 6 and 7 of POS Register 5 and bit 0 of POS Register 2 are defined by the architecture; all other bits within POS Registers 2 through 5 are available for adapter use.

Required Configuration Fields

The following configuration fields are required for all adapters.

Note: When CHRESET is driven active, adapters must set all fields to the default state.

Adapter ID Field

The Adapter ID field is a two-byte, read-only field contained in POS Register 0 and 1. Each adapter is assigned a unique two-byte adapter ID that is used for adapter identification. An adapter ID of hex 0000 indicates that the adapter is not ready; if an adapter is not present, the adapter ID will be read as hex FFFF.

Card Enable Field

The card enable field is a one-bit, read/write field; it is bit 0 in POS Register 2. When this field is set to 0, the adapter disables the Micro Channel interface except when responding to its setup cycles. When this field is set to 1, the adapter enables all of its Micro Channel interface. The default state of this field is 0.

Channel Check Field

The Channel Check field is a one-bit, read/write field that indicates the adapter has driven -CHCK active; it is bit 7 of POS Register 5. The adapter sets this field to 0 to indicate it has an exception condition, and the system master resets this field to 1 to reset the adapter after handling the error condition. If the adapter has driven -CHCK active, it must set this field to 0 except for address parity exceptions. If the system master resets this field to 1 and the adapter is still driving -CHCK active, the adapter must drive -CHCK inactive. If the adapter does not support driving the -CHCK signal active (does not support channel check) this field is always set to 1.

Note: If this field is set to 0 during a setup cycle, the adapter should not drive -CHCK active.

Conditionally-Required Configuration Fields

The following are the configuration fields that are required when the adapter supports a specified function.

The Channel Check Status Indicator field has a specific location and state because the system master must handle the channel-check condition. Other conditionally-required fields do not have a specific location within POS address space or a specific state.

Note: When CHRESET is driven active, adapters must set all fields to the default state.

Adapter I/O Address Select Field

The Adapter I/O Address Select field is a one- to three-bit field that selects the adapter address decode from the possible address ranges. These bits allow I/O address resolution for up to eight devices of one type in a system. However, if the total I/O address space needed to support the maximum number of devices exceeds 32 bytes, use the Device I/O Address Assignment field.

Adapter ROM/RAM Address Select Field

The Adapter ROM/RAM Address Select field is a four-bit, read/write field that determines the starting address of the adapter ROM/RAM address space for the adapter. The adapter address space is defined as the memory address space from hex 000C0000 to 000DFFFF. The four bits represent address bits A16 through A13, which corresponds to 16 consecutive 8KB blocks.

Note: Adapters that require more than 16KB in this memory space can cause addressing conflicts that cannot be resolved during system configuration.

Arbitration Level Field

The Arbitration Level field is a four-bit, read/write field that selects the arbitration level. All adapters that use the arbitration procedure (bursting and nonbursting) must support a selectable arbitration level.

Auto-Incrementing Enable Field

The Auto Incrementing Enable field is a one-bit, read/write field that enables or disables the automatic incrementing of POS Registers 6 and 7. The default state for this field is disable, which causes the adapter to not perform auto-incrementing. When enabled, it causes POS Registers 6 and 7 to automatically increment for each access to POS Register 3 or 4.

Channel Check Exception Reporting Field

The Channel Check Exception Reporting field is a one-bit, read/write field that selects either synchronous or asynchronous -CHCK exception reporting for channel non-parity or slave-dependent exception conditions. When enabled, these exceptions are reported with synchronous -CHCK . When disabled, these exceptions are reported by asynchronous -CHCK . The default state for this field is disabled.

Channel Check Status Indicator Field

The Channel Check Status Indicator field is a one-bit, read-only field that indicates if channel-check status is available; it is bit 6 of POS Register 5. The default state of this field is 1. This field is required if the Channel Check field is supported by the adapter.

When this field is a 1, it indicates that status for the channel-check condition is not available. When the field is 0 and the Channel Check field is 0, it indicates that POS Registers 6 and 7 contain the channel-check status or a pointer to the status. (If an adapter does not support -CHCK , bit 6 of POS register 5 can be used for other configuration information.) Data and Address Parity Enable Field The Data and Address Parity Enable field is a one-bit, read/write field that is required if the adapter supports address or data parity. This field enables address or data parity on the channel. The default state for this field is disabled. While disabled, the device does not drive either -DPAREN or -APAREN active, and does not check parity from the channel. This field can be a two-bit field to individually enable data and address parity.

Device I/O Address Assignment

The Device I/O Address Assignment field is a six-bit field that selects the I/O address of the adapter. The six bits represent bits 15 through 10 of the I/O address as shown in the following figure. All I/O devices with a total I/O-address-space requirement greater than 32 bytes must support this field.

The total I/O-address-space requirement for a particular type of device is:

The number of bytes of I/O address space required by one device multiplied by the maximum number of devices of the same type supported in one system.

Address bits 15, 14, and 13 must be in POS registers 2 through 5. Address bits 12, 11, and 10 can be in POS registers 2 through 5 or in the POS extension. The address bits in the POS extension must default to 1 at power on.

Matched Memory Enable Field

The Matched Memory Enable field is a one-bit, read/write field that enables or disables support for the matched-memory signals. The default state of this field is disable, which causes the memory adapter to use the default cycle of the Basic Transfer procedures. When the field is in the enable state, the adapter will support the matched-memory signals.

Selected Feedback Return Exception Enable Field

The Selected Feedback Return Exception Enable field is a one-bit, read/write field that selects whether or not a master reports select-feedback-return exceptions. When the field is in the enable state, the adapter reports select-feedback-return exceptions. When the field is in the disable state, the adapter does not report a select-feedback-return exception. The default state of this field is disable.

10 MHz Streaming Data Enable Field

The 10 MHz Streaming Data Enable field is a one-bit, read/write field that enables support for 10 MHz streaming data procedures. The default state of this field is disable, which causes the adapter to use the basic data transfer procedures. Adapters that support 10 MHz streaming data procedures must support this bit. When disabled, a slave must tri-state its streaming-data signals, and a master must tri-state -SD STROBE . When enabled, the 10 MHz streaming data procedure is supported.

20 MHz Streaming Data Enable Field

The 20 MHz Streaming Data Enable field is a one-bit, read/write field that enables support for 20 MHz streaming data procedures. The default state of this field is disable, which causes the adapter to not support 20 MHz streaming data transfer procedures. Adapters that support 20 MHz streaming data procedures must support this bit. When disabled, a slave must not drive -SDR(0,1) to the 00 or 10 state and a master must not activate both status signals after the first -SD STROBE activation. When enabled, the 20 MHz streaming data procedure is supported.

Optional Configuration Fields

The following configuration fields are optional.

Note: When CHRESET is driven active, adapters must set all fields to the default state.

Option Select Data Field

The Option Select Data field is four bytes of adapter unique information in POS Registers 2 through 5 that allow developers to customize configuration data for the specific adapter. Bit 0 of POS Register 2 and bits 7 and 6 of POS Register 5 are defined by the architecture; all other bits within the Option Select Data field are available for adapter configuration.

Fairness Feature Enable Field

The Fairness Feature Enable field is a one-bit, read/write field that enables or disables the fairness feature. The default state for this bit is enabled.

POS Subaddress Extension Field

The POS Subaddress Extension field is an optional, two-byte field that provides a method to extend the POS register space. It is contained in POS Registers 6 and 7 and is used as an index for all setup-cycle accesses to POS Registers 3 and 4. This field allows the subaddressing of up to 128KB of additional information for each adapter.

The POS extension is an extension to POS Registers 3 and 4 and is made up of two one-byte registers. An index of hex 0000 results in setup cycles accessing POS Register 3 and 4. All adapters supporting the POS extension must set the index to hex 0000 when CHRESET is driven active. The default value for this field is hex 0000.

Adapters supporting POS extension can use POS Registers 6 and 7 as an index register that is automatically incremented for each access to POS Register 3 or 4. Adapters supporting this feature use the Auto-Incrementing field to enable the feature.

When bits 6 and 7 in POS Register 5 are set to 0, reading POS Registers 6 and 7 will return the channel-check-status information. This information can be status or a pointer to the status.

The following is an example of how subaddressing could be used to store or access data in the POS extension.

Note: The amount of POS-extension information that can be supported is system dependent.

Status Information Field

The Status Information field is contained in POS Registers 6 and 7. The field is used by an adapter to indicate its channel-check status or as a pointer to channel-check status.

System Configuration Procedure

The system configuration procedure uses setup cycles to transfer adapter ID and adapter configuration data between the system master and adapters. The system configuration procedure is similar to the basic transfer procedure, except for the following:

Address Bus During Setup Cycles

During a setup cycle, a valid POS-register address is driven on the address bus; only address bits A(0-2) are decoded by the adapter. The address driven on the bus must not be the I/O address of any adapter.

The following figure shows the organization of the address space used by POS during setup. 

-CD           Address
SETUP  M/-IO  A2 A1 A0   Function
0      0       0  0  0   Adapter ID (Low Byte)
0      0       0  0  1   Adapter ID (High Byte)
0      0       0  1  0   Option Select Data Byte 1
0      0       0  1  1   Option Select Data Byte 2
0      0       1  0  0   Option Select Data Byte 3
0      0       1  0  1   Option Select Data Byte 4
0      0       1  1  0   Subaddress Extension/Channel Check Status (Low Byte)
0      0       1  1  1   Subaddress Extension/Channel Check Status (High Byte)

Card Enable Field During Setup Cycles

An adapter selected by -CD SETUP must enable its drivers, regardless of the state of the Card Enable field.

Channel Check Status During Setup Cycles

When -CHCK is driven active, the Channel Check field indicates that the adapter drove -CHCK active (except for address parity). The Channel Check, Channel Check Status Indicator, and Status Information fields (and channel-check status, if the field is used as a pointer) must remain unchanged until the system master resets the Channel Check field to 1 or until CHRESET is driven active.

-CD SETUP During Setup Cycles

During a setup cycle, only one adapter at a time is selected. The adapter is selected by an active -CD SETUP , not by an address decode or arbitration level.

CD CHRDY During Setup Cycles

CD CHRDY can be used to extend the setup cycle, as in the basic transfer procedure.

Exception Condition Reporting and Handling

An exception condition is an event (including errors) that disrupts normal processing by the master. Resolving an exception usually requires system intervention. Exception conditions are reported to the controlling master or the system master using either -CHCK or an interrupt.

Note: An adapter whose master function detects exception conditions reports the condition through its I/O slave function by driving -IRQ active.

Exception Conditions

The following types of exception conditions are supported:

Descriptions of each type are included in the following sections.

Channel Data and Address Parity Exceptions

Data and address parity support are optional features on the channel. This type of exception can occur during read or write operations. All participants that support data and address parity checking provide a POS bit (Data and Address Parity Enable field) to enable and disable this feature. The default state of this field is disable. When the Data and Address Parity Enable field is in the disable state, slaves disable checking data and address parity and do not activate -DPAREN during a data-transfer read cycle. Masters disable activation of -DPAREN and -APAREN and do not check data parity on the channel.

Note: Slaves do not disable the driving of -CHCK for non-parity exceptions (independent of the Data and Address Parity Enable field) and masters do not disable the detection of -CHCK .

The description of data and address parity support follows.

Data Parity

Data parity support is optional and allows the use of parity and non-parity adapters on the channel. For exceptions to be detected and reported, both the master and slave involved in the operation must support data parity. -DPAREN is activated by masters on write operations and by slaves on read operations. ( -DPAREN is activated by the data source only, and indicates the support of data parity.) The data parity bits, DPAR (0-3) , are provided at the same time as data on both write and read cycles, when parity is supported by the master and slave. Only the data bytes used during the data transfer need to have correct parity. For 64-bit streaming, the address parity bits are used during data transfers. -DPAREN is used to indicate that parity is valid on the address bus during 64-bit streaming data transfers. -APAREN remains inactive or is deactivated during the data portion of the transfer.

Data Parity Exception Handling

The following is a summary of how participants handle data-parity exception conditions.

Bus Master

During a read cycle a master that supports data parity checking and detects a parity error should do one of the following:

System Master

When a system master owns the channel and is enabled to support data parity, it must handle data parity errors.

DMA Controller

When a DMA controller that supports data parity detects a data parity error during a read cycle, it should record read data parity exception status and, if the DMA slave is selected, drive -TC active.

Alternatively, the DMA controller can drive -TC active on a subsequent operation with the DMA slave.

The system master reads the DMA controller and DMA slave exception status at the end of the DMA operation to determine if the operation completed successfully.

Slaves

When a selected slave detects a parity error during a write cycle, it should activate -CHCK and set bit 7 in POS Register 5 to 0 to indicate that an exception condition occurred. The slave determines what to do with the data.

Address Parity

Address parity support is optional and allows the use of parity and non-parity adapters on the channel.

For the exception to be detected and reported, both the master and slave involved in the operation must support address parity.

A controlling master that supports address parity drives -APAREN active to indicate that the parity is associated with the address. When a slave that supports address parity finds -APAREN active and an address parity error is detected, the slave is not selected. The slave includes address parity checking in its address decode. The following figure shows address parity timing requirements.

Slaves that support address parity must include parity checking in their address decode logic so that, when parity errors occur, they do not become selected and do not drive -CD SFDBK . Slaves check address parity for all data transfers that have -APAREN active. Slaves that support address parity check each address and drive -CHCK active when an address parity error is detected. I/O slaves check parity on all I/O addresses, and memory slaves check parity on all memory addresses. They do not set the channel check status bit in POS Register 5.

Note: A slave treating the address bus as a command should ensure address parity is good before allowing the command to execute.

Channel Non-Parity Exceptions

These exceptions are channel exceptions other than data and address parity exceptions. These exceptions can be signaled by the current slave or detected by the master.

Invalid -DS 16 RTN and -DS 32 RTN Combination

If the system master or a bus master detects an inactive -DS 16 RTN and an active -DS 32 RTN , it suspends the data transfer and posts an interrupt, indicating with interrupt status that the operation was not valid. Detecting the invalid operation is optional.

The DMA controller drives -TC active during the cycle of the detected exception when the DMA slave is selected, and records the status of the invalid operation. Alternatively, the DMA controller can drive -TC active on a subsequent operation with the DMA slave.

Selected Feedback Return Exception

Bus masters monitor -SFDBKRTN under control of a Selected Feedback Return Exception Enable field.

Masters that do not support -SFDBKRTN do not need this POS bit. When the Selected Feedback Return Exception Enable field is enabled and -SFDBKRTN is inactive, the bus master sets appropriate status, suspends the data transfer and interrupts the system master.

The DMA controller monitors -SFDBKRTN under control of a Selected Feedback Return Exception Enable field. DMA controllers that do not support -SFDBKRTN do not need this POS bit. When the Selected Feedback Return Exception Enable field is enabled and -SFDBKRTN is inactive, the DMA controller sets the appropriate status and, if a DMA slave is selected, drives -TC active for that cycle. Alternatively, the DMA controller can drive -TC active on a subsequent operation with the DMA slave.

Systems can monitor the -CD SFDBK signals, or -SFDBKRTN , under control of the Selected Feedback Return Exception Enable field. When the Selected Feedback Return Exception Enable field is enabled and a -CD SFDBK is not returned, the system monitor should set appropriate status and generate an interrupt.

These types of exceptions can occur during either read or write operations.

Note: Masters must record the state of -SFDBKRTN when a channel check is detected regardless of the state of the Select Feedback Return Exception Enable field.

Master and Slave Dependent Exceptions

Master- and slave-dependent exceptions are not related to the channel but to the participants. Reporting of this type of exception is specific to each participant and to the specific exception condition.

This type of exception can occur during either read or write operations. A channel check can also occur. Therefore, a master must monitor -CHCK for exceptions during both read and write operations.

This is required regardless of whether address parity or data parity are supported.

Master- and DMA slave-dependent exceptions should be reported with an interrupt. However, certain slave-dependent exceptions might require using -CHCK to report the exception. Examples of exceptions that could require using -CHCK are:

Channel Timeout Exception

If a controlling master or DMA slave fails to release the channel within 7.8 microseconds of -PREEMPT going active, the central arbitration control point can drive ARB/-GNT to the ARB state. In this state, the controlling master degates the address and data buses and all data transfer signals.

Note: Reporting and handling of this type of exception is system dependent.

Exception Reporting

A slave normally reports exceptions with synchronous -CHCK . A master normally reports exceptions with an interrupt and termination of current bus ownership. Exception reporting using -CHCK is described in the following information.

Exception Reporting using -CHCK

Exceptions detected by a slave or channel monitor are usually reported by activating a synchronous -CHCK . If -CHCK is activated, the system master or a bus master suspends processing and generates an interrupt. This interrupt invokes a utility program to handle the exception condition.

Any adapter that activates -CHCK sets bit 7 in POS Register 5 to a 0, to indicate the source of the exception in all cases except address parity errors. If multiple conditions can set -CHCK , the adapter can optionally set status information indicating the cause of the exception. The status or a pointer to it should be placed in POS Registers 6 and 7. Bit 6 in POS Register 5 is then set to 0 to indicate that status information is available. The system master can reset the -CHCK indication by setting a logical 1 into bit 7 in POS Register 5. Setting the bit to 0 will produce unpredictable results. Adapters that do not support -CHCK must ensure bit 7 in POS Register 5 is interpreted as a logical 1.

Synchronous and asynchronous reporting of exceptions using the -CHCK signal are supported. Both reporting methods are described in the following sections.

Synchronous -CHCK

Synchronous -CHCK is signaled by a slave or channel monitor with a pulse on -CHCK . The conditions that are reported with synchronous -CHCK are:

Note: Slaves or channel monitors that report channel non-parity or slave-dependent exceptions with synchronous -CHCK must support the Channel Check Exception Reporting field.

Asynchronous -CHCK

An asynchronous -CHCK is indicated by driving -CHCK active asynchronously to a data transfer. -CHCK remains active until reset by the system master. The adapter that activates an asynchronous -CHCK sets bit 7 in POS Register 5 to a 0. The asynchronous -CHCK is reset by the system master setting bit 7 in POS Register 5, to a 1 (in the adapter that activated -CHCK ). The time that asynchronous -CHCK remains active is system master dependent.

Because asynchronous exceptions are latched, -CHCK is detected during the reading of the adapter configuration registers to determine the source of the exception. System masters should ignore -CHCK while collecting status associated with the signaling of -CHCK .

The conditions that can be reported with asynchronous -CHCK are:

If the exception cannot be reported with an interrupt or a synchronous -CHCK and the condition would otherwise go undetected, the exception can be reported with an asynchronous -CHCK . Using asynchronous -CHCK can cause momentary suspension of all I/O activity and could require a system reset.

Exception Reporting Using Interrupts

If an interrupt is used to report an exception, status must be supplied to indicate the type of exception being reported.

Exception Handling

The following describes how participants handle -CHCK conditions.

Bus Master

The bus master monitors -CHCK when it is the controlling master. When the bus master detects -CHCK , it should do one of the following:

Data sent by the bus master after it detects -CHCK might not be received. Data received by the bus master after it detects -CHCK might not be valid.

System Master

The system master monitors -CHCK when it is the controlling master. If -CHCK is detected, the system master will handle the exception condition. The system master can monitor -CHCK at all other times also. The action taken is system dependent.

The method for handling exceptions is software dependent and will include setting the -CHCK status bit to 1 in participants that have activated -CHCK , if exception recovery is part of the action taken.

DMA Controller

A DMA controller monitors -CHCK when it is the controlling master. When it detects -CHCK active, the DMA controller should record channel-check status, record the state of -SFDBKRTN , and, if the DMA slave is selected, drive -TC active. Alternatively, the DMA controller can drive -TC active on a subsequent operation with the DMA slave.

The system master reads the DMA controller and DMA slave exception status, when the end of the DMA operation is signaled, to determine if the operation completed successfully.

Slaves

When a slave activates -CHCK , it must set bit 7 in POS Register 5 to a 0 (except for address parity checking). The system master, upon resolving the -CHCK exception, will reset the bit to a 1.

Select Feedback Exception Handling

A -SFDBKRTN exception occurs when the controlling master does not detect -SFDBKRTN active (or -CD SFDBK for system masters). Reporting of this exception is optional. However, all masters that receive -SFDBKRTN must record its state when an exception occurs. Reporting -SFDBKRTN exceptions is controlled by the Select Feedback Return Exception Enable field. If the master does not receive the signal, the POS field and the monitoring of the signal is not required.

Note: All masters that support address parity must receive -SFDBKRTN .

The following describes how participants handle a -SFDBKRTN exception.

Bus Master

A bus master that is enabled to report a -SFDBKRTN exception and does not receive a -SFDBKRTN should do one of the following:

The status provided with the interrupt includes the lack of -SFDBKRTN . Data sent by the bus master after it detects the lack of -SFDBKRTN might not be received. Data received by the bus master after it detects the lack of -SFDBKRTN might not be valid.

System Master

Reporting a -SFDBKRTN exception and handling the exception is system dependent.

DMA Controller

A DMA controller that is enabled to report a -SFDBKRTN exception and receives no -SFDBKRTN should record status and, if the DMA slave is selected, drive -TC active. Alternatively, the DMA controller can drive -TC active on a subsequent operation with the DMA slave.

At the end of the DMA operation the system master reads the DMA controller and DMA slave status to determine if the operation completed successfully.

Channel Reset

CHRESET is used to force all system functions and channel participants to a defined state. The following situations cause a channel reset.

CHRESET is active for a minimum amount of time, after all voltages in the system are within operating limits.

After a channel reset or a system power-on reset, the state of the Micro Channel buses and signals are as follows: 

                        System Power-On Reset  Channel Reset
                        ---------------------  ------------------
Buses and Signals       Adapter     System     Adapter    System
---------------------   ---------   -------    ---------  -------
Address Bus and         Tri-state   Initial    Tri-state  Unknown
  Associated Signals
Data Bus and            Tri-state   Initial    Tri-state  Unknown
  Associated Signals
Arbitration Bus and     Tri-state   Initial    Tri-state  Unknown
  Associated Signals
IRQ signal              Inactive    Initial    Inactive   Initial
Channel Check Signal    Inactive    Initial    Inactive   Initial
All Others              Inactive    Initial    Inactive   Unknown

Connector Definition

The channel provides all signal, power, and ground signals to adapters through 50-mil channel connectors.

The channel provides two basic types of connectors:

Pins 01 through 45 support 8-bit operations. Pins 46 and 47 are keys (physical notch). Pins 48 through 58 provide additional power and signals to support 16-bit operations. For 32-bit adapters that function in 16-bit connectors, pins 59 and 60 are keys; for 32-bit adapters that cannot function in 16-bit connectors, pins 59 and 60 are reserved. Pins 61 through 89 are used with pins 01 through 58 to support 32-bit operations.

The power and ground pins on side A of each connector are offset from side B by 2 pins, and every fourth pin on either side of each connector is an ac ground.

Video and matched-memory extensions to the basic 16- and 32-bit connectors are implemented on a system-by-system basis. For more information, see the technical reference for the specific system.

Note: Adapter designs should not extend the card-edge connector beyond the basic 16- or 32-bit connector unless the signals provided by the extension are used by the adapter.

All of the logic signal lines are transistor-transistor logic (TTL) compatible.

The following figure shows the basic types of channel connectors with optional extensions.

Warning: Any signals shown or described as "Reserved" should not be driven or received. These signals are reserved to allow compatibility with future implementations of the channel interface. Serious compatibility problems, loss of data, or permanent damage can result to features or the system, if these signals are misused.

Micro Channel Connector

The following figure shows the signals and the voltages assigned to the 32-bit channel connector. The 16-bit connector is a subset of the 32-bit connector consisting of pins 1 through 58. A key is provided at pin locations 46 and 47 for mechanical alignment. 

     SIGNAL      PIN      SIGNAL
-----------    -------    --------------
  AUDIO GND    B01 A01    -CD SETUP
      AUDIO    B02 A02    +MADE 24
        GND    B03 A03    GND
14.3Mhz OSC    B04 A04    +A 11
        GND    B05 A05    +A 10
      +A 23    B06 A06    +A 09
      +A 22    B07 A07    +5VDC
      +A 21    B08 A08    +A 08
        GND    B09 A09    +A 07
      +A 20    B10 A10    +A 06
      +A 19    B11 A11    +5VDC
      +A 18    B12 A12    +A 05
        GND    B13 A13    +A 04
      +A 17    B14 A14    +A 03
      +A 16    B15 A15    +5VDC
      +A 15    B16 A16    +A 02
        GND    B17 A17    +A 01
      +A 14    B18 A18    +A 00
      +A 13    B19 A19    +12VDC
      +A 12    B20 A20    -ADL
        GND    B21 A21    -PREEMPT
-IRQ 09 (2)    B22 A22    -BURST
    -IRQ 03    B23 A23    -12VDC
    -IRQ 04    B24 A24    +ARB 00
        GND    B25 A25    +ARB 01
    -IRQ 05    B26 A26    +ARB 02
    -IRQ 06    B27 A27    -12VDC
    -IRQ 07    B28 A28    +ARB 03
        GND    B29 A29    +ARB/-GNT
    -DPAREN    B30 A30    -TC
    +DPAR 0    B31 A31    +5VDC
      -CHCK    B32 A32    -S0
        GND    B33 A33    -S1
       -CMD    B34 A34    +M/-IO
  +CHRDYRTN    B35 A35    +12VDC
  -CD SFDBK    B36 A36    +CD CHRDY
        GND    B37 A37    +D 00
      +D 01    B38 A38    +D 02
      +D 03    B39 A39    +5VDC
      +D 04    B40 A40    +D 05
        GND    B41 A41    +D 06
   +CHRESET    B42 A42    +D 07
 -SD STROBE    B43 A43    GND
     -SDR 0    B44 A44    -DS 16 RTN
        GND    B45 A45    -REFRESH
        KEY    B46 A46    KEY
        KEY    B47 A47    KEY
      +D 08    B48 A48    +5VDC
      +D 09    B49 A49    +D 10
        GND    B50 A50    +D 11
      +D 12    B51 A51    +D 13
      +D 14    B52 A52    +12VDC
      +D 15    B53 A53    +DPAR 1
        GND    B54 A54    -SBHE
    -IRQ 10    B55 A55    -CD DS 16
    -IRQ 11    B56 A56    +5VDC
    -IRQ 12    B57 A57    -IRQ 14
        GND    B58 A58    -IRQ 15
-----------    -------    --------------
   RESERVED    B59 A59    RESERVED
   RESERVED    B60 A60    RESERVED
     -SDR 1    B61 A61    GND
      -MSDR    B62 A62    RESERVED
        GND    B63 A63    RESERVED
      +D 16    B64 A64    -SFDBKRTN
      +D 17    B65 A65    +12VDC
      +D 18    B66 A66    +D 19
        GND    B67 A67    +D 20
      +D 22    B68 A68    +D 21
      +D 23    B69 A69    +5VDC
    +DPAR 2    B70 A70    +D 24
        GND    B71 A71    +D 25
      +D 27    B72 A72    +D 26
      +D 28    B73 A73    +5VDC
      +D 29    B74 A74    +D 30
        GND    B75 A75    +D 31
      -BE 0    B76 A76    +DPAR 3
      -BE 1    B77 A77    +12VDC
      -BE 2    B78 A78    -BE 3
        GND    B79 A79    -DS 32 RTN
      +TR32    B80 A80    -CD DS 32
      +A 24    B81 A81    +5VDC
      +A 25    B82 A82    +A 26
        GND    B83 A83    +A 27
      +A 29    B84 A84    +A 28
      +A 30    B85 A85    +5VDC
      +A 31    B86 A86    -APAREN
        GND    B87 A87    +APAR 0
    +APAR 2    B88 A88    +APAR 1
    +APAR 3    B89 A89    GND
-----------    -------    --------------
  BACK SIDE               COMPONENT SIDE
-----------    -------    --------------

Adapter Physical Specifications

The following are the physical specifications for Micro Channel adapters; these adapters can be Type 3, Type 3 half-card, Type 5, or Type 9. The type number identifies the dimensions of the adapter.

Systems specify the adapter type that they support.

Adapter Size

The following are overall dimensions for Micro Channel adapters. Additional and more detailed information (plus tolerances) is available in Micro Channel Adapter Design. 
Type 3 Adapter
 * Card height - 3.475 in.
 * Card plus retainer length - 12.3 in.

Type 3 Half-card Adapter
 The Type 3 half card adapter does not require a retainer.
 * Card height - 3.475 in.
 * Card plus retainer length - 6.35 in.

Type 5 Adapter
 The Type 5 adapter does not require a retainer.
 * Card height - 4.825 in.
 * Card length - 13.1 in.

Type 9 Adapter
 The Type 9 adapter does not require a retainer.
 * Card height - 9.0 in.
 * Card length - 13.1 in.

Connector Spacing

 * Minimum Spacing from Card Center to Card Center - 0.85 in.
   (Maximum spacing is system dependent.)
 * Maximum Component Height (Measured from card surface.)
   A side (without electrical insulation) = 0.6 in
   A side (with electrical insulation) = 0.675 in
   B side = 0.105 in.

Electrical insulation is also required if the card bows in excess of 0.025 inch. Measure the bow at a point 0.1 inch from the top of the card and 5.75 inches from the connector end (rear) of the card.

Power

The following figures list the minimum available load current for each voltage present on each connector. Some systems can provide more current than the amount specified below. For more information, refer to the system-specific technical manual.

Minimum current available for the Type 3 adapter. 

Supply       Minimum Available Current    Minimum Available Current
Voltage      Per 16-Bit Connector         Per 32-Bit Connector
+  5.0 Vdc   1.6 A                        2.0 A
+ 12.0 Vdc   0.175 A                      0.175 A
- 12.0 Vdc   0.040 A                      0.040 A

Minimum current available for the Type 5 adapter 

Supply       Minimum Available Current    Minimum Available Current
Voltage      Per 16-Bit Connector         Per 32-Bit Connector
+  5.0 Vdc   3.12 A                       3.12 A
+ 12.0 Vdc   0.25 A                       0.25 A
- 12.0 Vdc   0.10 A                       0.10 A

Minimum current available for the type 9 adapter 

Supply       Minimum Available Current    Minimum Available Current
Voltage      Per 16-Bit Connector         Per 32-Bit Connector
+  5.0 Vdc   5.0 A                        7.0 A
+ 12.0 Vdc   0.7 A                        0.7 A
- 12.0 Vdc   0.2 A                        0.2 A

Voltage Regulation

The voltage regulation at the channel connector is shown in the following table. 

Voltage     Pins                                         Tolerance
Ground      A3,B3,B5,B9,B13,B17,B21,B25,B29,             N/A
            B33,B37,B41,A43,B45,B50,B54,B58              N/A
            A61,B63,B67,B71,B75,B79,B83,B87,A89,         N/A
+  5.0 Vdc  A7,A11,A15,A31,A39,A48,A56,A69,A73,A81,A85   + 5% - 4.5%
+ 12.0 Vdc  A19,A35,A52,A65,A77,                         + 5% - 4.5%
- 12.0 Vdc  A23,A27                                      + 9.5% - 10%

The tolerance includes all power distribution losses in both power and ground planes, up to the pins of the channel connector. It does not include the drop due to the connector (30 milliohm maximum per contact), or the drop due to distribution within the adapter.

Refer to "Update for the IBM Personal System/2 Hardware Technical Reference - Architectures", IBM Publication S10G-6466, for the complete Micro Channel Architecture document.