MULTIBUS I


        The Multibus standard was originally developed by Intel. It
specified four busses, called the Multibus System Bus, the I/O Expansion
Bus (iSBX), the Execution Bus (iLBX) and the Multichannel I/O Bus.
The multibus system bus was adopted as IEEE 796, and the iSBX bus
was adopted as IEEE P959.
        Multibus is popular in industrial systems, and while it is a fairly
old bus, it is still in common use. The original design dates back to the
early 70's. In the early 80's, Intel created Mutlibus II, which was later
adopted as IEEE-STD 1296. Multibus II will not be covered in this article.
Because of the existance of Multibus II, the original Multibus is often
referred to as Multibus I.
        This article is not intended to be a thorough coverage of the
standard. It is designed to give hobbyists and designers a general
overview of the bus and how it works, so that they may be able to
design their own multibus cards. For a more information, the Intel
"Multibus Handbook" is an excellent resource. The copy I have is dated
1983, and has an order number 210883-001. I have not contacted Intel to
see if this book (or a later version) is still in print. The actual bus
standards are also available from Intel. Contact Intel for more
information (http://www.intel.com).
        Multibus, Multichannel, iSBX, and iLBX are trademarks of Intel
Corporation.


MUTLIBUS OVERVIEW

The following diagram shows a typical multibus system.
Note: You will need a fixed space font (all the characters have
the same spacing) to be able to properly view the diagram.


   Specialized I/O
          |
      ==iSBX Bus==       Local Memory
          |                |
          |----====iLBX Bus======
          |
          |                               I/O
          |     Communication   Other      |
         CPU    Interface       I/O       CPU--Dual Port Ram
          |      |               |         |        |
      ============Multibus System Bus=================


        Note that there are many other combinations possible. The above
diagram is given only to show how the various busses may all be used
in a single system. The important concepts are the use of multiple bus
masters, multiple data paths, and the use of dual port ram as a method
of communication throughout the system (either cpu may access the ram,
making it an ideal method for transmitting data back and forth).


----------------------------------------------------------------------------
MUTLIBUS SYSTEM BUS
----------------------------------------------------------------------------

        Multibus cards have two connectors. The larger is labled P1 and
is used for the multibus system bus. P2 is used for the execution bus,
although it also contains two address lines used by the system bus.
I am using Intel's notation for the bus signals, with the exception of
the address and data lines. Intel numbers these in hex and uses the
designations ADR and DAT. I have numbered them in decimal, and use the
simpler A and D for address and data respectively.


P1 connector pinouts:

1  GND                  2  GND
3  +5                   4  +5
5  +5                   6  +5
7  +12                  8  +12
9  -5/Reserved [A]      10 -5/Reserverd [A]
11 GND                  12 GND
13 *BCLK                14 *INIT
15 *BPRN                16 *BPRQ
17 *BUSY                18 *BREQ
19 *MRDC                20 *MWTC
21 *IORC                22 *IOWC
23 *XACK                24 *INH1
25 *LOCK                26 *INH2
27 *BHEN                28 *A16
29 *CBREQ               30 *A17
31 *CCLK                32 *A18
33 *INTA                34 *A19
35 *INT6                36 *INT7
37 *INT4                38 *INT5
39 *INT2                40 *INT3
41 *INT0                42 *INT1
43 *A14                 44 *A15
45 *A12                 46 *A13
47 *A10                 48 *A11
49 *A8                  50 *A9
51 *A6                  52 *A7
53 *A4                  54 *A5
55 *A2                  56 *A3
57 *A0                  58 *A1
59 *D14                 60 *D15
61 *D12                 62 *D13
63 *D10                 64 *D11
65 *D8                  66 *D9
67 *D6                  68 *D7
69 *D4                  70 *D5
71 *D2                  72 *D3
73 *D0                  74 *D1
75 GND                  76 GND
77 Reserved             78 Reserved
79 -12                  80 -12
81 +5                   82 +5
83 +5                   84 +5
85 GND                  86 GND

The system bus also uses the following pins on the P2 connector:
55 *A22                 56 *A23
57 *A20                 58 *A21

* indicates active low

[A] IEEE-796 reserves pins 9 and 10. Older systems may have -5 volts on
both of these pins.


Signal Descriptions:

+5, +12. -5, -12: Voltage Supply Lines
A0-A23: Address Lines. Note that these lines are active low (a low voltage
        indicates a logic 1).
D0-D15: Data Lines. Note that these lines are active low (a low voltage
        indicates a logic 1).
BCLK: Bus Clock. 50% duty cycle. This clock is not constant. It may be
        stopped, single cycled, or used at a varying frequency. Any bus
        master in a system should be able to drive this clock.
        The maximum frequency is 10 MHz. This signal may be completely
        independent from CCLK, although in practical systems, both CCLK
        and BCLK will usually be derived from the same source.
CCLK: Constant Clock. 50% duty cycle. Frequency varies, but is fixed for
        a given system. 10 MHz is typical.
INIT: Initialize. This causes all cards in the system to initialize. It
        is asserted on power-up. Bus masters may assert this signal.
        This signal may also be driven by a panel switch (debounced).
LOCK: This signal prevents access to dual port memory used as a shared
        resource between processors. Bus masters will drive this signal low
        between read and write operations during a Read-Modify-Write (RMW)
        cycle.
BREQ: Bus Request. This is used by bus masters to request control of the
        bus. This signal is not shared between cards, but instead goes
        to a parallel arbitration circuit on the motherbaord.
BPRN: Bus Priority In.
BPRO: Bus Priority Out.
BUSY: Bus Busy.
CBRQ: Common Bus Request.
MRDC: Memory Read Command.  Used to indicate the type of bus transfer.
MWTC: Memroy Write Command.  Used to indicate the type of bus transfer.
IORC: I/O Read Command. Used to indicate the type of bus transfer.
IOWC: I/O Write Command. Used to indicate the type of bus transfer.
XACK: Transfer Acknowledge.  Asserted by the slave to acknowledge the
        transfer, so that the bus master knows to end the transfer cycle.
INH(x): Inhibit.
BHEN: Byte High Enable. Indicates a 16 bit transfer.
INT(x): Interrupt request.
INTA: Interrupt Acknowledge.


DATA TRANSFERS

        Data transfers may be 8 or 16 bits. The command lines are used to
indicate the type of transfer. 8 bit transfers use the lower 8 data lines
for both even and odd byte transfers. 16 bit transfers use all 16 data lines.


Multibus Sytem Bus Read/Write Timing Diagram:

                                     ___________________________
A0-A23, BHEN [A]              ------<___________________________>----

Command Line                  __________                _____________
(MRDC, MWTC, IORC, IOWC)                |______________|

                                                 ___________
D0-D15 [B], Read              ------------------<___________>--------

                                     ___________________________
D0-D15 [B], Write             ------<___________________________>----

                             ____________________            ________
XACK                                             |__________|


            Address setup time      |---| 50 ns min
            Data hold time (read)                      |----| 60 ns min
            XACK removed after command line removed    |----| 65 ns max


[A] BHEN will be inactive (high) for an 8 bit transfer, and active
(low) for a 16 bit transfer.

[B] D0-D7 only for 8 bit transfers


        The bus master first drives the address lines. BHEN will be driven
active for 16 bit transfers. For a write operation, the data lines are
also driven using the same timing as the address lines. The command line
is driven next, indicating the type of bus transfer (IORC for an I/O
read, IOWC for an I/O write, MRDC for a memory read, MWTC for a memory
write).  For a read operation, the slave device places the data onto the
bus and drives the acknowledge line (XACK). The master then reads the
data from the bus. For a write operation, the slave device reads the data
from the bus and drives the acknowledge signal to indicate that it has
read the data, and that the master no longer needs to drive the address
and data lines.
        A bus timout occurs when the slave device does not acknowledge
the transfer. The timout mechanism prevents the master from waiting
indefinately for a response that it may never receive. The minimum time
before the master is allowed to timout is 1 millisecond.

INHIBIT

        The inhibit lines are used during memory operations (MRDC and
MWTC). An inhibit line is asserted by a slave device to inhibit another
slave device's bus activity during the memory operation. The inhibit
system is based on priorities, and slave devices may be top prioriy,
middle priority, or bottom priority. A lower priority device will be
inhibited by a higher priority device. A middle priority device uses
only INH1, which will inhibit activity by a bottom priority device. A top
priority device would use INH2 to inhibit a middle priority device, and
also would use INH1 to inhibiy a bottom priority device at the same time.
        Inhibit signals are ignored during I/O operations.

LOCKING THE BUS

        The bus may be locked during a read-modify-write exchange. This
prevents other processors from accessing the memory between the read and
the write, which could cause problems in multi-processor environments.
To lock the bus, the current bus master must assert LOCK 100 ns before
the read command line is removed, and must hold this line active until
at least 100 ns after the falling edge of the command line for the last
locked cycle. LOCK must be released within 12 microseconds from its
assertion (in other words, you can't lock the bus for more than 12 micro-
seconds at a time).

INTERRUPTS

        The interrupt request lines (INT0 - INT7) are level triggered,
active low. INT0 has the highest priority, and INT7 has the lowest.
        Interrupts may be implimented on Mutlibus systems using either
bus vectored or non-bus vectored interrupts. In a non-bus vectored system,
the bus master does not need to access the bus for the interrupt vector.
It simply responds to the interrupt in the appropriate manner, then
continues processing as normal (the exact function of interrupts depends
on the particular system).
        Bus vectored interrupts transfer the interrupt vector over the
bus during the interrupt acknowledge process. In this case, the bus master
generates two INTA signals.

Bus Vectored Interrupt Timing:

         _____                                          ___________
INT(x)        |________________________________________|

         __________              _____              _______________
INTA               |____________|     |____________|

                                      ______________
A0-A23   ----------------------------<______________>--------------
                                           [A]

                                          __________
D0-D7    --------------------------------<__________>--------------
                                            [B]

         ____________________________________     _________________
XACK                                         |___|

[A] The address lines contain the interrupt address while the second
INTA signal is active.

[B] The data lines now contain the interrupt vector.

        Some systems may use a third INTA pulse to transfer a second
interrupt vector byte. Systems are permitted to use either a single byte
interrupt vector, or a 2 byte interrupt vector, but not both in the
same system.

        It is possible to have both bus vectored and non-bus vectored
interrupts on the same system.

BUS MASTERS:



----------------------------------------------------------------------------
I/O EXPANSION BUS (iSBX)
----------------------------------------------------------------------------

        The iSBX bus was designed with small I/O cards in mind. It allows
a small daughter board, like a serial I/O or parallel I/O port for example,
to be attached to a multibus card.

iSBX connector pinouts:

1   +12                 2   -12
3   GND                 4   +5
5   RESET               6   MCLK
7   MA2                 8   MPST*
9   MA1                 10  reserved
11  MA0                 12  MINTR1
13  IOWRT*              14  MINTR0
15  IORD*               16  MWAIT*
17  GND                 18  +5
19  MD7                 20  MCS1*
21  MD6                 22  MCS0*
23  MD5                 24  reserved
25  MD4                 26  TDMA
27  MD3                 28  OPT1
29  MD2                 30  OPT0
31  MD1                 32  MDACK*
33  MD0                 34  MDRQT
35  GND                 36  +5
37  MD14                38  MD15
39  MD12                40  MD13
41  MD10                42  MD11
43  MD8                 44  MD9

* - indicates an active low signal.

+5, +12, -12: Voltage supply lines
GND: Ground
IORD: I/O Read Command line.
IOWRT: I/O Write Command line.
MA0-MA2: Module Address lines.
MCS0, MCS1: Module Chip Select Lines. Note that these lines may be active
        when not required to be valid.
MD0-MD15: Module Data Lines. MD8-MD15 are only used on 16 bit systems.
MDACK: Module DMA Acknowledge.
MCLK: Module Clock.
MDRQT: Module DMA Request.
MINTRO, MINTR1: Module Interrupt lines.
MPST: Module Present.
MWAIT: Module Wait.
OPT0, OPT1: Option lines.
RESET: Reset.
TDMA: Terminate DMA.

----------------------------------------------------------------------------
EXECUTION BUS (iLBX)
----------------------------------------------------------------------------

        The iLBX bus uses the P2 (smaller) connector, and also may use
an auxiliary connector (called the JX connector) located on the top right
side of the board.


P2 connector pinouts

1  DB0                  2  DB1
3  DB2                  4  DB3
5  DB4                  6  DB5
7  DB6                  8  DB7
9  GND                  10 DB8
11 DB9                  12 DB10
13 DB11                 14 DB12
15 DB13                 16 DB14
17 DB15                 18 GND
19 AB0                  20 AB1
21 AB2                  22 AB3
23 AB4                  24 AB5
25 AB6                  26 AB7
27 GND                  28 AB8
29 AB9                  30 AB10
31 AB11                 32 AB12
33 AB13                 34 AB14
35 AB15                 36 GND
37 AB16                 38 AB17
39 AB18                 40 AB19
41 AB20                 42 AB21
43 AB22                 44 AB23
45 GND                  46 *ACK
47 BHEN                 48 R/W
49 *ASTB                50 *DSTB
51 *SMRQ                52 *SMACK
53 *LOCK                54 GND
55 A22 [A]              56 A23[A]
57 A20 [A]              58 A21[A]
59 Reserved             60 TPAR

* Active Low
[A] These are the upper address lines used by the system bus. They are
        not used by the expansion bus.


----------------------------------------------------------------------------
MULTICHANNEL I/O BUS
----------------------------------------------------------------------------



(C) Copyright 1997 by Mark Sokos

This article may be freely copied and distributed, provided that no fee
is charged for its duplication or use. I make every attempt to insure
that the information is accurate, but I'm only human, so mistakes may
be present. If you find any, please let me know.

The latest version of this article may be found at:
http://users.desupernet.net/sokos/


References:
"Multibus Handbook", Intel Corp. Order #210883-001